Semiconductor package embedded with a plurality of chips

Patent metadata

Field	Value
Publication number	US-9966359-B2
Application number	US-201514969241-A
Country	US
Kind code	B2
Filing date	Dec 15, 2015
Priority date	Sep 21, 2015
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

A semiconductor package may be provided. The semiconductor package may include a substrate. The semiconductor package may include a first semiconductor chip flip-chip bonded to a first surface of the substrate. The semiconductor package may include second semiconductor chips respectively flip-chip bonded to portions of the first surface of the substrate adjacent to both ends of the first semiconductor chip. The semiconductor package may include a third semiconductor chip solder-jointed to the first surface of the substrate covering the first semiconductor chip and portions of the second semiconductor chips.

First claim

What is claimed is:

1. A semiconductor package comprising:
a substrate;
a first semiconductor chip flip-chip bonded to a first surface of the substrate;
second semiconductor chips respectively flip-chip bonded to portions of the first surface of the substrate adjacent to both ends of the first semiconductor chip in a first direction; and
a third semiconductor chip solder-jointed to the first surface of the substrate as to completely cover the first semiconductor chip and partially covering portions of the second semiconductor chips,
wherein the third semiconductor chip has a first active surface facing the first surface of the substrate, the first semiconductor chip and the second semiconductor chips, and a first bottom surface facing away from the first active surface, and comprises a plurality of first bonding pads which are arranged in the first direction along both ends of a second direction substantially perpendicular to the first direction of the first active surface and the first connection members formed on the first bonding pads,
wherein the third semiconductor chip is directly jointed to the first surface of the substrate by the first connection members.

2. The semiconductor package according to claim 1 , wherein the substrate comprises:
pluralities of first to third bond fingers arranged on the first surface;
a plurality of ball lands arranged on a second surface facing away from the first surface; and
solder resists respectively formed on the first surface and the second surface in such a way as to expose the first to third bond fingers and the ball lands.

3. The semiconductor package according to claim 2 ,
wherein the first bond fingers are arranged in the second direction along both ends of a center portion of the first surface of the substrate on which the first semiconductor chip is disposed,
wherein the second bond fingers are arranged in the second direction along both ends of the respective portions of the first surface of the substrate on which the second semiconductor chips are respectively disposed, and
wherein the third bond fingers are arranged in the first direction along both ends of a portion of the first surface of the substrate over which the third semiconductor chip is disposed.

4. The semiconductor package according to claim 1 , wherein the first semiconductor chip comprises an SoC (system-on-chip) which has a substantially quadrangular plate shape.

5. The semiconductor package according to claim 1 , wherein the first semiconductor chip has a second active surface facing the first surface of the substrate and a second bottom surface facing away from the second active surface, and comprises a plurality of second bonding pads arranged in the second direction substantially perpendicular to the first direction along both ends of the second active surface.

6. The semiconductor package according to claim 5 , wherein the first semiconductor chip further comprises second connection members formed on the second bonding pads.

7. The semiconductor package according to claim 6 , wherein the second connection members comprise bumps.

8. The semiconductor package according to claim 1 , wherein each of the second semiconductor chips has a second active surface facing the first surface of the substrate and a second bottom surface facing away from the second active surface, and comprises a plurality of second bonding pads arranged in the second direction substantially perpendicular to the first direction along both ends of the second active surface.

9. The semiconductor package according to claim 8 , wherein each of the second semiconductor chips further comprises second connection members formed on the second bonding pads.

10. The semiconductor package according to claim 9 , wherein the second connection members comprise bumps.

11. The semiconductor package according to claim 9 , wherein the second connection members comprising the bumps are arranged with a pitch of approximately 50 μm to approximately 100 μm.

12. The semiconductor package according to claim 9 , wherein the first semiconductor chip has a third active surface facing the first surface of the substrate and a third bottom surface facing away from the third active surface, and comprises a plurality of third bonding pads arranged in the second direction substantially perpendicular to the first direction along both ends of the third active surface, wherein the first semiconductor chip further comprises third connection members formed on the third bonding pads, wherein the third connection members have substantially the same diameter as the second connection members, and wherein the second connection members have a pitch shorter than the third connection members.

13. The semiconductor package according to claim 1 , wherein the first connection members comprise solder balls.

14. The semiconductor package according to claim 13 ,
wherein the first connection members comprising the solder balls are arranged with a pitch of approximately 120 μm to approximately 450 μm.

15. The semiconductor package according to claim 1 ,
wherein the first semiconductor chip has a second active surface facing the first surface of the substrate and a second bottom surface facing away from the second active surface, and comprises a plurality of second bonding pads arranged in the second direction substantially perpendicular to the first direction along both ends of the second active surface,
wherein the first semiconductor chip further comprises second connection members formed on the second bonding pads,
wherein the first connection members are arranged with a pitch greater than a pitch of the second connection members.

16. The semiconductor package according to claim 1 , further comprising:
an encapsulation member formed on the first surface of the substrate to cover the first to third semiconductor chips; and
a plurality of external connection members formed on a second surface of the substrate facing away from the first surface.

17. The semiconductor package according to claim 1 ,
wherein the first semiconductor chip includes a logic chip,
wherein the second semiconductor chips include memory chips, and
wherein the third semiconductor chip comprises a memory chip.

18. The semiconductor package according to claim 1 ,
wherein each of the second semiconductor chips have a substantially rectangular plate shape having a length shorter than the first semiconductor chip in the first direction, and having substantially the same length as the first semiconductor chip in the second direction.

Assignees

• Sk Hynix Inc

Inventors

• Lee Sang Eun
• Ko Eun
• Park Yong Jae

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title