Proximity coupling of interconnect packaging systems and methods

Patent metadata

Field	Value
Publication number	US-9595513-B2
Application number	US-201414556450-A
Country	US
Kind code	B2
Filing date	Dec 1, 2014
Priority date	Dec 1, 2014
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.

First claim

We claim:

1. A semiconductor package assembly comprising:
a substrate having bond pads;
a first semiconductor die disposed adjacent the substrate, the first semiconductor die having a first coupling face that faces away from the substrate;
a second semiconductor die having a second coupling face and bond pads at the second coupling face, the second semiconductor die stacked on the first semiconductor die such that the second coupling face faces the first coupling face;
a proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face and a second conductive pad on the second coupling face spaced from the first conductive pad by a gap distance and aligned with the first conductive pad; and
an electrical connector positioned laterally apart from the proximity coupling interconnect and extending between one of the bond pads of the second semiconductor die and one of the bond pads of the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad,
wherein the first coupling face has a first passivation layer extending beyond a height of the first conductive pad and having a first opening exposing the first conductive pad,
wherein the second coupling face has a second passivation layer extending beyond a height of the second conductive pad and having a second opening exposing the second conductive pad,
wherein the first and second passivation layers define the gap distance between the first conductive pad and the second conductive pad, and wherein the proximity coupling interconnect comprises a capacitive coupling interconnect or an inductive coupling interconnect.

2. The semiconductor package assembly of claim 1 , wherein the electrical connector comprises a solder interconnect and the proximity coupling interconnect comprises a capacitive coupling interconnect.

3. The semiconductor package assembly of claim 1 , wherein the electrical connector comprises a solder interconnect and the proximity coupling interconnect comprises an inductive coupling interconnect.

4. The semiconductor package assembly of claim 1 , wherein gap distance is about 1 microns to about 10 microns.

5. The semiconductor package assembly of claim 1 , wherein the first semiconductor die comprises a memory die.

6. The semiconductor package assembly of claim 1 , wherein the second semiconductor die comprises a logic die.

7. The semiconductor package assembly of claim 1 , further comprising a spacer positioned on the substrate and having a third coupling face that faces away from the substrate, the spacer being spaced laterally from the first semiconductor die, and the second semiconductor die being stacked over the spacer such that the second coupling face overlaps a portion of the third coupling face.

8. The semiconductor package assembly of claim 7 , wherein the assembly has a plurality of first semiconductor dies, and the spacer comprises one of the first semiconductor dies.

9. The semiconductor package assembly of claim 8 , further comprising a second proximity coupling interconnect between the second semiconductor die and each of the first semiconductor dies, and wherein each of the proximity coupling interconnects comprises a first conductive pad on one of the first semiconductor dies aligned with a corresponding second conductive pad in the second semiconductor dies.

10. The semiconductor package assembly of claim 1 , further comprising a thermal lid coupled to the substrate and enclosing the first semiconductor die and the second semiconductor die.

11. The semiconductor package assembly of claim 10 , further comprising a thermal fill material disposed between the thermal lid and the first semiconductor die and the second semiconductor die.

12. The semiconductor package assembly of claim 1 , further comprising an underfill material disposed between the second semiconductor die and the substrate, the underfill material surrounding the electrical connector.

13. The semiconductor package assembly of claim 1 , wherein the electrical connector provides electrical communication between second semiconductor die and the substrate.

14. The semiconductor package assembly of claim 1 , wherein the second semiconductor die overlaps only a portion of the first semiconductor die, and another portion of the second semiconductor die extends laterally beyond the first semiconductor die and over at least a set of bond pads on the substrate.

15. A semiconductor package assembly comprising:
a first semiconductor die having a first coupling face;
a second semiconductor die having a second coupling face that faces the first coupling face, the second coupling face having a first portion that overlaps the first coupling face and a second portion that does not overlap the first coupling face;
a proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first pad on the first coupling face and a second pad on the second coupling face, wherein the first pad is aligned with and spaced apart from the second pad by an open space; and
a spacing structure projecting from the second portion of the second coupling face of the second semiconductor die, the spacing structure defining a gap between the first pad and the second pad,
wherein the first coupling face has a first passivation layer extending beyond a height of the first pad and having a first opening exposing the first pad,
wherein the second coupling face has a second passivation layer extending beyond a height of the second pad and having a second opening exposing the second pad, and wherein the proximity coupling interconnect comprises a capacitive coupling interconnect or an inductive coupling interconnect.

16. The semiconductor package assembly of claim 15 , wherein the spacing structure comprises a solder interconnect spaced laterally apart from the proximity coupling interconnect and extending between the second portion of the second coupling face and a substrate.

17. The semiconductor package assembly of claim 15 , wherein the spacing structure comprises a solder interconnect extending between the second portion of the second coupling face and a third semiconductor die comprising a through-silicon via (TSV), the solder interconnect providing electrical communication between the second semiconductor die and the TSV of the third semiconductor die.

18. The semiconductor package assembly of claim 17 , wherein the first semiconductor die is stacked over a fourth semiconductor die, wherein the third semiconductor die and the fourth semiconductor die are disposed over a substrate and laterally spaced apart from one another.

19. The semiconductor package assembly of claim 15 , wherein the proximity coupling interconnect comprises a capacitive coupling interconnect.

20. The semiconductor package assembly of claim 15 , wherein the proximity coupling interconnect comprises an inductive coupling interconnect.

21. The semiconductor package assembly of claim 15 , wherein first pad is spaced from the second pad by a distance from about 1 microns to about 10 microns.

Assignees

• Micron Technology Inc

Inventors

• Fogal Rich
• Fay Owen R

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title