Semiconductor interconnect structures

Patent metadata

Field	Value
Publication number	US-9064872-B2
Application number	US-201414323246-A
Country	US
Kind code	B2
Filing date	Jul 3, 2014
Priority date	Dec 4, 2012
Publication date	Jun 23, 2015
Grant date	Jun 23, 2015

Abstract

Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etch stop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etch stop layer, and an interconnect feature may pass through the second insulator layer and the conformal etch stop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.

First claim

What is claimed is:

1. A semiconductor device, comprising a conductive interconnect feature connecting a first conductive feature with a second conductive feature, the conductive interconnect feature passing through a conformal intervening layer and partially landing on the first conductive feature, wherein the unlanded portion of the conductive interconnect feature rests on but does not penetrate the conformal intervening layer.

2. The device of claim 1 wherein the conformal intervening layer conforms to a protruding portion of the first conductive feature that extends beyond an insulator layer.

3. The device of claim 1 , wherein the first conductive feature is included in a first insulator layer, and the second conductive feature is included in a second insulator layer, and the first insulator layer, conformal intervening layer, and second insulator layer are arranged in a stack.

4. The device of claim 1 , wherein a protruding portion of the first conductive feature extends beyond an insulator layer, the protruding portion having a rounded corner with which the conductive interconnect feature connects.

5. The device of claim 1 , wherein the first conductive feature is included in a first insulator layer, and the ratio of first insulator layer etch rate to the first conductive feature etch rate for a given etch process is greater than 3.

6. The device of claim 1 , wherein a portion of the first conductive feature at least partially protrudes from a first insulator layer, and the conformal intervening layer is at least partially on and conforms to the protruding portion.

7. The device of claim 6 , further comprising an additional insulator layer at least partially on the conformal intervening layer, wherein the conductive interconnect feature further passes through the additional insulator layer.

8. The device of claim 7 , wherein the additional insulator layer comprises a flowable dielectric material.

9. The device of claim 8 , wherein the flowable dielectric material is one of a flowable carbide or flowable nitride.

10. The device of claim 1 , wherein the first conductive feature is included in a first insulator layer, and the second conductive feature is included in a second insulator layer, and at least one of the first and second insulator layers comprises an ultra-low dielectric material having a dielectric constant below that of silicon dioxide, and the conformal intervening layer comprises a dielectric material having a higher dielectric constant than the ultra-low dielectric material.

11. A mobile computing system comprising the device of claim 1 .

12. A microprocessor comprising the device of claim 1 .

13. A memory circuit comprising the device of claim 1 .

14. A semiconductor structure, comprising:
a first insulator layer having a first conductive feature;
a second insulator layer having a second conductive feature protruding therefrom;
a conformal dielectric layer at least partially on and conforming to the protruding portion of the second conductive feature; and
a conductive interconnect feature connecting the first conductive feature with the second conductive feature, the conductive interconnect feature passing through the conformal dielectric layer and partially landing on the second conductive feature so as to provide an unlanded portion of the conductive interconnect feature, wherein the unlanded portion of the conductive interconnect feature rests on but does not penetrate the conformal intervening layer.

15. The structure of claim 14 , wherein the first insulator layer, conformal dielectric layer, and second insulator layer are arranged in a stack.

16. The structure of claim 14 , wherein the protruding portion of the second conductive feature has a rounded corner with which the conductive interconnect feature connects.

17. The structure of claim 14 , wherein the ratio of first insulator layer etch rate to the first conductive feature etch rate for a given etch process is greater than 3.

18. A semiconductor structure, comprising:
a conductive interconnect feature connecting a first conductive feature with a second conductive feature, the conductive interconnect feature passing through a conformal dielectric layer and partially landing on the first conductive feature so as to provide an unlanded portion of the conductive interconnect feature, wherein the unlanded portion of the conductive interconnect feature rests on but does not penetrate the conformal intervening layer; and
an insulator layer at least partially on the conformal dielectric layer, wherein the conductive interconnect feature further passes through the insulator layer.

19. The structure of claim 18 , wherein the additional insulator layer comprises a flowable dielectric material.

20. The structure of claim 19 , wherein the flowable dielectric material is one of a flowable carbide or flowable nitride.

Assignees

• Intel Corp
• Intel Corp

Inventors

• Boyanov Boyan
• Singh Kanwal
• Clarke James
• Myers Alan

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title