Semiconductor interconnect structures

Patent metadata

Field	Value
Publication number	US-9455224-B2
Application number	US-201514746315-A
Country	US
Kind code	B2
Filing date	Jun 22, 2015
Priority date	Dec 4, 2012
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etchstop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etchstop layer, and an interconnect feature may pass through the second insulator layer and the conformal etchstop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.

First claim

What is claimed is:

1. An integrated circuit device, comprising a conductive interconnect feature connecting to a first conductive feature, the conductive interconnect feature at least partially within a first insulator layer and passing through a conformal intervening layer distinct from the first insulator layer and partially landing on the first conductive feature, wherein the unlanded portion of the conductive interconnect feature does not penetrate the conformal intervening layer, wherein:
the first conductive feature is included in a second insulator layer, and the first insulator layer, conformal intervening layer, and second insulator layer are arranged in a stack, the conformal intervening layer being between the first and second insulator layers, and
the first insulator layer comprises a first dielectric material having a first dielectric constant, and the conformal intervening layer comprises a second dielectric material having a second dielectric constant, and the second dielectric constant is higher than the first dielectric constant.

2. The device of claim 1 wherein the conformal intervening layer conforms to a protruding portion of the first conductive feature that extends beyond a second insulator layer, the conformal intervening layer being between the first and second insulator layers.

3. The device of claim 1 , wherein the conductive interconnect feature is landed on an upper edge of the first conductive feature, the upper edge being at least one of rounded and tapered inward relative to a lower portion of the first conductive feature.

4. The device of claim 1 , wherein the first dielectric constant is below that of silicon dioxide, and the second dielectric constant is above that of silicon dioxide.

5. The device of claim 1 , wherein the second insulator layer comprises the same dielectric material as the first insulator layer.

6. A mobile computing system comprising the device of claim 1 .

7. A microprocessor comprising the device of claim 1 .

8. A memory circuit comprising the device of claim 1 .

9. An integrated circuit device, comprising:
a conductive interconnect feature connecting to a first conductive feature, the conductive interconnect feature at least partially within a first insulator layer and passing through a conformal intervening layer distinct from the first insulator layer and partially landing on the first conductive feature, wherein the unlanded portion of the conductive interconnect feature does not penetrate the conformal intervening layer; and
an additional insulator layer at least partially on the conformal intervening layer, wherein the additional insulator layer is distinct from the first insulator layer, and the conductive interconnect feature further passes through the additional insulator layer.

10. The device of claim 9 , wherein the additional insulator is a flowable carbide or flowable nitride, and the additional insulator layer is about the same height as a high point of the underlying conformal intervening layer, the high point corresponding to a portion of the first conductive feature that protrudes beyond a layer in which it is positioned.

11. The device of claim 9 , wherein the first conductive feature is included in a second insulator layer, and the first insulator layer, conformal intervening layer, additional insulator layer, and second insulator layer are arranged in a stack, the conformal intervening layer being between the first and second insulator layers.

12. The device of claim 11 , wherein the first insulator layer comprises a first dielectric material having a first dielectric constant, and the conformal intervening layer comprises a second dielectric material having a second dielectric constant, and the second dielectric constant is higher than the first dielectric constant.

13. An integrated circuit device, comprising a conductive interconnect feature connecting to a first conductive feature, the conductive interconnect feature at least partially within a first insulator layer and passing through a conformal intervening layer distinct from the first insulator layer and partially landing on the first conductive feature, wherein the unlanded portion of the conductive interconnect feature does not penetrate the conformal intervening layer, wherein the first conductive feature is included in a second insulator layer, and at least one of the first and second insulator layers comprises an ultra-low dielectric material having a dielectric constant below that of silicon dioxide, and the conformal intervening layer comprises a dielectric material having a dielectric constant higher than the dielectric constant of the ultra-low dielectric material.

14. A semiconductor structure, comprising a conductive interconnect feature at least partially within an insulator layer and that passes through a conformal dielectric layer distinct from the insulator layer to partially land on an underlying conductor thereby providing landed and unlanded portions of the conductive interconnect feature, wherein the unlanded portion is offset from the landed portion and does not penetrate the conformal dielectric layer, wherein the conductor is protruding from a second insulator layer distinct from the conformal dielectric layer, the conformal dielectric layer being between the first and second insulator layers and conforming to the conductor.

15. A memory circuit comprising the structure of claim 14 .

16. The structure of claim 14 , wherein the insulator layer, conformal dielectric layer, and second insulator layer are arranged in a stack.

17. The structure of claim 14 , wherein the conductive interconnect feature is landed on an upper edge of the protruding portion of the conductor, the upper edge being tapered inward relative to a corresponding lower edge of the protruding portion of the conductor.

18. The structure of claim 14 , wherein the insulator layer etches faster than the conformal dielectric layer for a given etch scheme.

19. A semiconductor structure, comprising:
a conductive interconnect feature at least partially within an insulator layer and that passes through a conformal dielectric layer distinct from the insulator layer to partially land on an underlying conductor thereby providing landed and unlanded portions of the conductive interconnect feature, wherein the unlanded portion is offset from the landed portion and does not penetrate the conformal dielectric layer; and
an additional insulator layer distinct from and between the conformal dielectric layer and the insulator layer.

20. The structure of claim 19 , wherein the additional insulator layer is a flowable carbide or flowable nitride.

Assignees

• Intel Corp

Inventors

• Boyanov Boyan
• Singh Kanwal Jit
• Clarke James
• Myers Alan

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title