Method of manufacturing semiconductor integrated circuit device

Patent metadata

Field	Value
Publication number	US-9960075-B2
Application number	US-201715497740-A
Country	US
Kind code	B2
Filing date	Apr 26, 2017
Priority date	Jul 1, 2014
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate having a main surface including a first region and a second region, the first region having a first portion, a second portion, a third portion, a fourth portion and a fifth portion sequentially,
a first trench in the substrate at the second portion;
a first insulation film formed in the first trench;
a second insulation film formed on the first insulation film;
a third insulation film formed on the main surface of the substrate at the fourth portion;
a gate electrode formed on the second insulation film and the third insulation film;
a first semiconductor region formed in the main surface of the substrate at a side of the second insulation film at the first portion;
a second semiconductor region formed in the main surface of the substrate at a side of the gate electrode at the fifth portion;
a second trench in the substrate at the second region;
a fourth insulation film formed in the second trench; and
a fifth insulation film formed on the fourth insulation film,
wherein the first insulation film and the second insulation film extend on the main surface of the substrate at the third portion, and
wherein the gate electrode is formed over the first insulation film and the second insulation film at the third portion contiguous to the first trench.

2. A semiconductor device according to claim 1 , wherein the first insulation film and the fourth insulation film are silicon oxide films.

3. A semiconductor device according to claim 1 , wherein the second insulation film and the fifth insulation film are silicon oxide films.

Assignees

• Renesas Electronics Corp

Inventors

• Shinohara Masaaki
• Iida Satoshi

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10W10/0121

  in regions recessed from the surface, e.g. in trenches or grooves · CPC title

• H10W10/13

  formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI] · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014 Primary

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title