Method of manufacturing semiconductor integrated circuit device

Patent metadata

Field	Value
Publication number	US-9418996-B2
Application number	US-201615053551-A
Country	US
Kind code	B2
Filing date	Feb 25, 2016
Priority date	Jul 1, 2014
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film.
The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate having a main surface including a first region for a high breakdown MOSFET and a second region for a low breakdown MOSFET, the first region having a first portion, a second portion and a third portion sequentially, the second region having a fourth portion and a fifth portion adjacently;
a first shallow trench in the substrate at the first portion;
a first insulation film formed in the first shallow trench;
a second insulation film formed on the main surface of the substrate at the third portion;
a first gate electrode formed on the first insulation film and the second insulation film;
a first semiconductor region and a second semiconductor region formed in the main surface of the substrate at both sides of the first gate electrode; and
a second shallow trench in the substrate at the fourth portion;
a third insulation film formed in the second shallow trench;
a second gate electrode formed over the main surface of the substrate at the fifth portion,
wherein the first insulating film extends on the main surface of the substrate at the second portion,
herein the third insulating film is formed in the second shallow trench at the fourth portion and does not extend on the main surface of the substrate in the fifth portion, and
wherein the depth of the first shallow trench is equal to that of the second shallow trench.

2. A semiconductor device according to claim 1 ,
wherein the depth of the first insulating film at the second portion is greater than that of the third insulating film at the fifth portion.

3. A semiconductor device according to claim 1 ,
wherein the first gate electrode is formed over the first insulating film at the second portion contiguous to the first shallow trench.

4. A semiconductor device according to claim 1 ,
wherein the first insulating film and the third insulating film are silicon oxide films.

5. A semiconductor device according to claim 1 ,
herein the first gate electrode and the second gate electrode are poly-silicon electrodes.

Assignees

• Renesas Electronics Corp

Inventors

• Shinohara Masaaki
• Iida Satoshi

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10W10/0121

  in regions recessed from the surface, e.g. in trenches or grooves · CPC title

• H10W10/13

  formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI] · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014 Primary

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title