Method of manufacturing semiconductor integrated circuit device

Patent metadata

Field	Value
Publication number	US-9305824-B2
Application number	US-201514738846-A
Country	US
Kind code	B2
Filing date	Jun 13, 2015
Priority date	Jul 1, 2014
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film.
The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a hard mask film over a first main surface of a semiconductor wafer and making a first opening in the hard mask film in a first region over the first main surface;
(b) forming sidewall insulating films on the side surfaces of the hard mask film of the first opening, respectively;
(c) forming a first shallow trench in a semiconductor region surface of the first main surface in the first opening, with the hard mask film and the sidewall insulating films as masks;
(d) after the step (c), oxidizing at least an exposed portion of an inner surface of the first shallow trench and the semiconductor region surface of the first main surface in the first opening;
(e) after the step (d), filling the first shallow trench and the first opening with an insulating film;
(f) after the step (e), removing the insulating film outside the first shallow trench so as to leave the insulating film outside the first shallow trench in the first opening and thereby forming a drain offset STI insulating film inside and outside the first shallow trench, and
(g) after the step (f), forming a first gate electrode from an upper portion of a gate insulating film in a first active region contiguous to the drain offset STI insulating film to an upper portion of the drain offset insulating film.

2. The method of manufacturing a semiconductor integrated circuit device according to claim 1 , further comprising the step of:
(h) after the step (c) but before the step (d), making a second opening in the hard mask film in a second region over the first main surface and thereby forming a second shallow trench in a semiconductor region surface of the first main surface in the second opening;
wherein in the step (d), at least an exposed portion of the inner surface of the second shallow trench is oxidized;
wherein in the step (e), the second shallow trench and the second opening are filled with an insulating film;
wherein in the step (f), the insulating film outside the second shallow trench is removed to form an interelement STI insulating film in the second shallow trench, and
wherein in the step (g), a second gate electrode is formed over the gate insulating film in a second active region contiguous to the second shallow trench.

3. The method of manufacturing a semiconductor integrated circuit device according to claim 1 ,
wherein the hard mask film has a silicon nitride-based insulating film as a main component film thereof.

4. The method of manufacturing a semiconductor integrated circuit device according to claim 3 , further comprising the step of:
(i) after the step (f) but before the step (g), removing the silicon nitride-based insulating film.

5. The method of manufacturing a semiconductor integrated circuit device according to claim 1 ,
wherein the hard mask film has a polysilicon film as an upper half main portion thereof.

6. The method of manufacturing a semiconductor integrated circuit device according to claim 1 ,
wherein a width of the first shallow trench at the time when the step (d) is started is greater than a width between the sidewall insulating films at the time when the step (c) is completed.

7. The method of manufacturing a semiconductor integrated circuit device according to claim 1 , further comprising the step of:
(j) after the step (c) but before the step (d), removing the sidewall insulating films.

8. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a hard mask film over a first main surface of a semiconductor wafer and making a first opening in the hard mask film in a first region over the first main surface;
(b) forming sidewall insulating films over the side surfaces of the hard mask film of the first opening, respectively;
(c) forming a first shallow trench in a semiconductor region surface of the first main surface in the first opening, with the hard mask film and the sidewall insulating films as masks;
(d) after the step (c), making a second opening in the hard mask film in a second region over the first main surface and forming a second shallow trench in a semiconductor region surface of the first main surface in the second opening;
(e) after the step (d), oxidizing at least an exposed portion of an inner surface of the first shallow trench, an inner surface of the second shallow trench, and the semiconductor region surface of the first main surface in the first opening;
(f) after the step (e), filling the first shallow trench, the second shallow trench, the first opening, and the second opening with an insulating film;
(g) after the step (f), removing the insulating film outside the first shallow trench and the second shallow trench so as to leave the insulating film outside the first shallow trench in the first opening and thereby forming a drain offset STI insulating film inside and outside the first shallow trench and forming an interelement STI insulating film in the second shallow trench, and
(h) after the step (g), forming a first gate electrode from an upper portion of a gate insulating film in a first active region contiguous to the drain offset STI insulating film to an upper portion of the drain offset insulating film and forming a second gate electrode over a gate insulating film in a second active region contiguous to the second shallow trench.

9. The method of manufacturing a semiconductor integrated circuit device according to claim 8 ,
wherein the hard mask film has a silicon nitride-based insulating film as a main component film thereof.

10. The method of manufacturing a semiconductor integrated circuit device according to claim 9 , further comprising the step of:
(i) after the step (g) but before the step (h), removing the silicon nitride-based insulating film.

11. The method of manufacturing a semiconductor integrated circuit device according to claim 8 ,
wherein the hard mask film has a polysilicon film as an upper half main portion thereof.

12. The method of manufacturing a semiconductor integrated circuit device according to claim 8 ,
wherein a width of the first shallow trench at the time when the step (e) is started is greater than a width between the sidewall insulating films at the time when the step (c) is completed.

13. The method of manufacturing a semiconductor integrated circuit device according to claim 8 , further comprising the step of:
(j) after the step (c) but before the step (e), removing the sidewall insulating films.

14. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a hard mask film over a first main surface of a semiconductor wafer and making a first opening in the hard mask film in a first region over the first main surface;
(b) forming sidewall insulating films on the side surfaces of the hard mask film of the first opening, respectively;
(c) after the step (b), forming a second opening in the hard mask film in a second region over the first main surface;
(d) forming a first shallow trench in a semiconductor region surface of the first main surface in the first opening and forming a second shallow trench in a semiconductor region surface of the first main surface in the second opening, with the hard mask film and the sidewall insulating films as masks;
(e) after the step (d), oxidizing an exposed portion of an inner surface of the first shallow trench, an inner surface of the second shallow trench, and the semiconductor region surface of the first main surface in the first opening;
(f) after the step (e), filling

Assignees

• Renesas Electronics Corp

Inventors

• Shinohara Masaaki
• Iida Satoshi

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10W10/0121

  in regions recessed from the surface, e.g. in trenches or grooves · CPC title

• H10W10/13

  formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI] · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014 Primary

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title