Method for manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-9685561-B2
Application number	US-201615096632-A
Country	US
Kind code	B2
Filing date	Apr 12, 2016
Priority date	Jun 18, 2010
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

An object is to provide a semiconductor device having good electrical characteristics. A gate insulating layer having a hydrogen concentration less than 6×10 20 atoms/cm 3 and a fluorine concentration greater than or equal to 1×10 20 atoms/cm 3 is used as a gate insulating layer in contact with an oxide semiconductor layer forming a channel region, so that the amount of hydrogen released from the gate insulating layer can be reduced and diffusion of hydrogen into the oxide semiconductor layer can be prevented. Further, hydrogen present in the oxide semiconductor layer can be eliminated with the use of fluorine; thus, the hydrogen content in the oxide semiconductor layer can be reduced. Consequently, the semiconductor device having good electrical characteristics can be provided.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device comprising the steps of:
forming a conductive layer over a substrate;
forming a first insulating layer using a gas comprising SiH 4 over the conductive layer;
forming a second insulating layer using a gas comprising SiF 4 over the first insulating layer; and
forming an oxide semiconductor layer over and in contact with the second insulating layer,
wherein a fluorine concentration in a part of the first insulating layer is less than 1×10 20 atoms/cm 3 , and
wherein a hydrogen concentration in a part of the second insulating layer is less than 6×10 20 atoms/cm 3 and a fluorine concentration in the part of the second insulating layer is greater than 1×10 21 atoms/cm 3 .

2. The method for manufacturing a semiconductor device according to claim 1 , further comprising heating the oxide semiconductor layer in an inert gas at a temperature greater than or equal to 100° C. and less than or equal to 400° C.

3. The method for manufacturing a semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

4. The method for manufacturing a semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises indium, tin, and zinc.

5. The method for manufacturing a semiconductor device according to claim 1 , wherein the oxide semiconductor layer includes a crystal.

6. The method for manufacturing a semiconductor device according to claim 1 , wherein the substrate comprises a silicon wafer.

7. The method for manufacturing a semiconductor device according to claim 1 , wherein the conductive layer comprises copper.

8. A method for manufacturing a semiconductor device comprising the steps of:
forming a first conductive layer over a substrate;
forming a first insulating layer using a gas comprising SiH 4 over the first conductive layer;
forming a second insulating layer using a gas comprising SiF 4 over the first insulating layer;
forming an oxide semiconductor layer over and in contact with the second insulating layer;
forming a second conductive layer over and in contact with the oxide semiconductor layer; and
forming a third insulating layer using a gas comprising SiF 4 over and in contact with the oxide semiconductor layer and the second conductive layer,
wherein a fluorine concentration in a part of the first insulating layer is less than 1×10 20 atoms/cm 3 ,
wherein a hydrogen concentration in a part of the second insulating layer is less than 6×10 20 atoms/cm 3 and a fluorine concentration in the part of the second insulating layer is greater than 1×10 21 atoms/cm 3 , and
wherein a hydrogen concentration in a part of the third insulating layer is less than 6×10 20 atoms/cm 3 and a fluorine concentration in the part of the third insulating layer is greater than or equal to 1×10 20 1×10 21 atoms/cm 3 .

9. The method for manufacturing a semiconductor device according to claim 8 , further comprising heating the oxide semiconductor layer in an inert gas at a temperature greater than or equal to 100° C. and less than or equal to 400° C.

10. The method for manufacturing a semiconductor device according to claim 8 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

11. The method for manufacturing a semiconductor device according to claim 8 , wherein the oxide semiconductor layer comprises indium, tin, and zinc.

12. The method for manufacturing a semiconductor device according to claim 8 , wherein the oxide semiconductor layer includes a crystal.

13. The method for manufacturing a semiconductor device according to claim 8 , wherein the substrate comprises a silicon wafer.

14. The method for manufacturing a semiconductor device according to claim 8 , wherein the second conductive layer comprises copper.

15. The method for manufacturing a semiconductor device according to claim 8 , wherein each of the first conductive layer and the second conductive layer comprises copper.

Assignees

• Semiconductor Energy Lab
• Semiconductor Energy Laboratories Co Ltd

Inventors

• Ichijo Mitsuhiro
• Endo Toshiya
• Suzuki Kunihiko

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10D30/6758

  characterised by the insulating substrates · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title