Critical dimension shrink through selective metal growth on metal hardmask sidewalls

US9953916B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9953916-B2
Application numberUS-201715423923-A
CountryUS
Kind codeB2
Filing dateFeb 3, 2017
Priority dateJun 1, 2015
Publication dateApr 24, 2018
Grant dateApr 24, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.

First claim

Opening claim text (preview).

What is claimed is: 1. A self-aligned via structure, comprising: a ILD layer disposed over a metal wiring layer; a trench within the ILD layer, a bottom surface of the trench being substantially parallel to a top surface of the metal wiring layer and having a first width; a via extending through the ILD layer and into a portion of the metal wiring layer, a vertical wall of the via oriented substantially perpendicular to the bottom surface of the trench and having a second width; wherein the second width of the via is smaller than the first width of the trench. 2. The self-aligned via structure of claim 1 , further comprising a barrier metal lining the via and the trench within the ILD layer and the metal wiring layer. 3. The self-aligned via structure of claim 2 , further comprising copper filling the trench and the via. 4. The self-aligned via structure of claim 1 , wherein the first width is in a range from about 5 nm to about 50 nm. 5. The self-aligned via structure of claim 4 , wherein the second width is in a range from about 25 nm to about 70 nm. 6. The self-aligned via structure of claim 1 , wherein the metal wiring layer is copper or a copper alloy. 7. The self-aligned via structure of claim 1 , wherein the metal wiring layer is manganese, manganese alloys, cobalt, cobalt alloys, tungsten, tungsten alloys, or any combination thereof. 8. The self-aligned via structure of claim 1 , wherein the first width is in a range from about 10 nm to about 30 nm. 9. The self-aligned via structure of claim 1 , wherein the via and the trench further comprise a barrier metal layer liner and a copper filling. 10. The self-aligned via structure of claim 9 , wherein the barrier metal layer liner is tantalum, tantalum nitride, titanium nitride, titanium tungstate, or a combination thereof. 11. A self-aligned via structure, comprising: a ILD layer disposed over a metal wiring layer; a trench within through the ILD layer, a bottom surface of the trench being substantially parallel to a top surface of the metal wiring layer and having a first width; a via extending through the ILD layer and into a portion of the metal wiring layer, a vertical wall of the via oriented substantially perpendicular to the bottom surface of the trench and having a second width; wherein the second width of the via is smaller than the first width of the trench, and the trench and the via comprise a barrier metal layer and a metal. 12. The self-aligned via structure of claim 11 , further comprising a barrier metal lining the via and the trench within the ILD layer and the metal wiring layer. 13. The self-aligned via structure of claim 12 , further comprising copper filling the trench and the via. 14. The self-aligned via structure of claim 11 , wherein the first width is in a range from about 5 nm to about 50 nm. 15. The self-aligned via structure of claim 14 , wherein the second width is in a range from about 25 nm to about 70 nm. 16. The self-aligned via structure of claim 11 , wherein the metal wiring layer is copper or a copper alloy. 17. The self-aligned via structure of claim 11 , wherein the metal wiring layer is manganese, manganese alloys, cobalt, cobalt alloys, tungsten, tungsten alloys, or any combination thereof. 18. The self-aligned via structure of claim 11 , wherein the first width is in a range from about 10 nm to about 30 nm. 19. The self-aligned via structure of claim 11 , wherein the via and the trench further comprise a barrier metal layer liner and a copper filling. 20. The self-aligned via structure of claim 19 , wherein the barrier metal layer liner is tantalum, tantalum nitride, titanium nitride, titanium tungstate, or a combination thereof.

Assignees

Inventors

Classifications

  • H10P50/73Primary

    using masks for insulating materials · CPC title

  • Barrier, adhesion or liner layers · CPC title

  • using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

  • involving partial etching of via holes · CPC title

  • involving multiple stacked pre-patterned masks · CPC title

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Frequently asked questions

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What does patent US9953916B2 cover?
A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via patte…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10P50/73. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 24 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).