Methods for fabrication interconnect structures with functional components and electrical conductive contact structures on a same level

Patent metadata

Field	Value
Publication number	US-9236298-B2
Application number	US-201514717387-A
Country	US
Kind code	B2
Filing date	May 20, 2015
Priority date	Sep 8, 2011
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

An electronic device includes an interlevel dielectric layer formed over a substrate and has a first set of openings and a second set of openings formed through the interlevel dielectric layer. The substrate includes conductive areas. A conductive contact structure is formed in the first set of openings in the interlevel dielectric layer to make electrical contact with the conductive areas of the substrate. A functional component is formed in the second set of openings in the interlevel dielectric layer and occupies a same level as the conductive contact structure.

First claim

What is claimed is:

1. A method, comprising:
forming an interlevel dielectric layer over a substrate;
patterning the interlevel dielectric layers to form openings therein;
blocking a first set of the openings with a block mask;
forming functional components in a second set of openings;
planarizing the surface of the functional components and the block mask in the first set of the openings;
removing the block mask to recover the first set of openings in the interlevel dielectric layer; and
filling the first set of openings with an electrically conductive fill material to form electrically conductive contacts which occupy a same level as the functional components.

2. The method as recited in claim 1 , wherein forming functional components includes forming at least one of a transistor device, a memory element, a capacitor or a diode in the second set of openings.

3. The method as recited in claim 1 , further comprising forming a permanent antireflective coating (ARC) on the substrate and performing an ARC open process to make electrical connections to the substrate.

4. The method as recited in claim 1 , further comprising forming a conducting material over the interlevel dielectric layer and connecting the conductive material to the functional component.

5. The method as recited in claim 1 , wherein blocking a first set of the openings with a block mask includes:
forming a sacrificial patternable dielectric layer over a top surface of the interlevel dielectric layer and in the openings;
patterning the sacrificial patternable dielectric layer to remove the sacrificial patternable dielectric layer from the second set of the openings and leaving the sacrificial patternable dielectric layer as the block mask in the first set of the openings; and
curing the sacrificial patternable dielectric layer on the top surface of the interlevel dielectric layer and in the first set of the openings to convert the sacrificial patternable dielectric layer into a cured dielectric layer.

6. The method as recited in claim 5 , wherein curing includes one or more of a thermal cure, an electron beam cure, an ultraviolet cure, an ion beam cure, a plasma cure, a microwave cure or any combination thereof.

7. The method as recited in claim 5 , wherein forming a sacrificial patternable dielectric layer includes forming the sacrificial patternable dielectric layer from a photo-patternable low-k (PPLK) material.

8. The method as recited in claim 7 , wherein the photo-patternable low-k (PPLK) material includes at least one of a polymer, a copolymer, a blend including at least two of any combination of polymers and/or copolymers, wherein the polymers include one monomer and the copolymers include at least two monomers and wherein the monomers of the polymers and the monomers of the copolymers are selected from: a siloxane, silane, carbosilane, oxycarbosilane, silsesquioxane, alkyltrialkoxysilane, tetra-alkoxysilane, unsaturated alkyl substituted silsesquioxane, unsaturated alkyl substituted siloxane, unsaturated alkyl substituted silane, an unsaturated alkyl substituted carbosilane, unsaturated alkyl substituted oxycarbosilane, carbosilane substituted silsesquioxane, carbosilane substituted siloxane, carbosilane substituted silane, carbosilane substituted carbosilane, carbosilane substituted oxycarbosilane, oxycarbosilane substituted silsesquioxane, oxycarbosilane substituted siloxane, oxycarbosilane substituted silane, oxycarbosilane substituted carbosilane, and oxycarbosilane substituted oxycarbosilane.

9. The method as recited in claim 1 , wherein forming functional components includes forming the functional components in a contact opening volume for a given feature size of a device technology within a height of the interlevel dielectric layer.

10. A method, comprising:
forming an interlevel dielectric layer over a substrate;
patterning the interlevel dielectric layer to form openings therein;
forming a sacrificial patternable dielectric layer over a top surface of the interlevel dielectric layer and in the openings of the interlevel dielectric layer;
patterning the sacrificial patternable dielectric layer to remove the sacrificial patternable dielectric layer from a second set of the openings and leaving the sacrificial patternable dielectric layer as a block mask in a first set of the openings;
curing the sacrificial patternable dielectric layer on the top surface of the interlevel dielectric layer and in the first set of the openings to convert the sacrificial patternable dielectric layer into a cured dielectric layer;
forming functional components in the second set of openings;
planarizing a surface of the functional components and the block mask in the first set of the openings;
removing the cured dielectric layer to recover the first set of openings in the interlevel dielectric layer; and
filling the first set of openings with an electrically conductive fill material to form electrically conductive contacts which occupy a same level as the functional components.

11. The method as recited in claim 10 , wherein forming functional components includes forming at least one of a transistor device, a memory element, a capacitor or a diode.

12. The method as recited in claim 10 , wherein forming functional components includes forming the functional components in a contact opening volume for a given feature size of a device technology within a height of the interlevel dielectric layer.

13. The method as recited in claim 10 , wherein forming a sacrificial patternable dielectric layer includes forming the sacrificial patternable dielectric layer from a photo-patternable low-k (PPLK) material.

14. The method as recited in claim 13 , wherein the photo-patternable low-k (PPLK) material includes at least one of a polymer, a copolymer, a blend including at least two of any combination of polymers and/or copolymers, wherein the polymers include one monomer and the copolymers include at least two monomers and wherein the monomers of the polymers and the monomers of the copolymers are selected from: a siloxane, silane, carbosilane, oxycarbosilane, silsesquioxane, alkyltrialkoxysilane, tetra-alkoxysilane, unsaturated alkyl substituted silsesquioxane, unsaturated alkyl substituted siloxane, unsaturated alkyl substituted silane, an unsaturated alkyl substituted carbosilane, unsaturated alkyl substituted oxycarbosilane, carbosilane substituted silsesquioxane, carbosilane substituted siloxane, carbosilane substituted silane, carbosilane substituted carbosilane, carbosilane substituted oxycarbosilane, oxycarbosilane substituted silsesquioxane, oxycarbosilane substituted siloxane, oxycarbosilane substituted silane, oxycarbosilane substituted carbosilane, and oxycarbosilane substituted oxycarbosilane.

15. The method as recited in claim 10 , further comprising forming a permanent antireflective coating (ARC) on the substrate and performing an ARC open process to make electrical connections to the substrate.

16. The method as recited in claim 10 , wherein curing includes one or more of a thermal cure, an electron beam cure, an ultraviolet cure, an ion beam cure, a plasma cure, a microwave cure or any combination thereof.

17. The method as recited in claim 10 , further comprising forming a top electrically conductive material over the interlevel dielectric layer and connecting the top electrically conductive material to the functional component.

Assignees

• Globalfoundries Us 2 Llc
• Globalfoundries Inc

Inventors

• Lin Qinghuang
• Pfeiffer Dirk

Classifications

• H10P95/08

  Planarisation of organic insulating materials · CPC title

• H10P95/00 Primary

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/0554

  of nanotubes or nanowires · CPC title

• H10W20/4462

  Carbon or carbon-containing materials, e.g. graphene · CPC title