Substrate-less stackable package with wire-bond interconnect

Patent metadata

Field	Value
Publication number	US-9953914-B2
Application number	US-201615042034-A
Country	US
Kind code	B2
Filing date	Feb 11, 2016
Priority date	May 22, 2012
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are unconvered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer.

First claim

The invention claimed is:

1. A method for making a microelectronic unit, comprising:
forming a plurality of wire bonds on a conductive bonding surface of a metallic structure, the wire bonds having bases joined to the conductive bonding surface and end surfaces disposed away from the conductive bonding surface;
forming a dielectric layer over at least a portion of the conductive bonding surface and over first portions of the wire bonds, the first portions including the bases thereof having the dielectric layer formed thereover for covering the first portions of the wire bonds, second portions of the wire bonds including the end surfaces thereof not covered by the dielectric layer; and
patterning the metallic structure to form conductive elements separated from one another by the dielectric layer for having the bases of the wire bonds disposed on the conductive elements.

2. The method of claim 1 , wherein at least some of the wire bonds are formed with the end surfaces thereof displaced in one or more lateral directions away from the bases thereof.

3. The method of claim 1 , wherein:
the bases are in a first pattern having a first minimum pitch; and
the second portions of the wire bonds are in a second pattern having a second minimum pitch greater than the first minimum pitch.

4. The method of claim 1 , wherein:
the bases are in a first pattern having a first minimum pitch; and
the second portions of the wire bonds are in a second pattern having a second minimum pitch less than the first minimum pitch.

Assignees

• Invensas Corp

Inventors

• Mohammed Ilyas

Classifications

• H10W90/752

  between stacked chips · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/271

  the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement · CPC title