Stacked multi-chip integrated circuit package

Patent metadata

Field	Value
Publication number	US-8963339-B2
Application number	US-201213647375-A
Country	US
Kind code	B2
Filing date	Oct 8, 2012
Priority date	Oct 8, 2012
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

A multi-chip integrated circuit (IC) package is provided which is configured to protect against failure due to warpage. The IC package may comprise a substrate, a level-one IC die and a plurality of level-two IC dies. The level-one IC die having a surface that is electrically coupled to the substrate. The plurality of level-two IC dies is stacked above the level-one IC die. The plurality of level-two IC dies may each have an active surface that is electrically coupled to the substrate. The plurality of level-two IC dies may be arranged side by side such that the active surfaces of the plurality of level-two IC dies are positioned substantially in a same plane. Relative to a single die configuration, the level-two IC dies are separated thereby inhibiting cracking, peeling and/or other potential failures due to warpage of the IC package.

First claim

What is claimed is:

1. A multi-chip integrated circuit (IC) package, comprising:
a substrate;
a level-one IC die having a surface that is electrically coupled to the substrate; and
a plurality of level-two IC dies stacked above the level-one IC die, the plurality of level-two IC dies each having an active surface that is electrically coupled to the substrate, the plurality of level-two IC dies arranged side by side such that the active surfaces of the plurality of level-two IC…

Assignees

• Qualcomm Inc

Inventors

• He Dongming
• Bao Zhongping
• Huang Zhenyu

Classifications

• H10W90/756

  Electricity · mapped topic

• H10W90/754

  Electricity · mapped topic

• H10W90/736

  Electricity · mapped topic

• H10W90/734

  Electricity · mapped topic

• H10W90/732

  Electricity · mapped topic