Semiconductor device with reduced via resistance

Patent metadata

Field	Value
Publication number	US-2016197010-A1
Application number	US-201615070411-A
Country	US
Kind code	A1
Filing date	Mar 15, 2016
Priority date	Jul 24, 2014
Publication date	Jul 7, 2016
Grant date	—

Abstract

A method of fabricating a semiconductor interconnect structure by providing a semiconductor structure that includes two dielectric layers. The first dielectric layer has an embedded electrically conductive structure. A second dielectric layer is located above the first dielectric layer. The second dielectric layer and the first dielectric layer have a segment of a dielectric capping layer and a segment of a metal capping layer located between them. The segment of the dielectric capping layer is horizontally planar with the segment of the metal capping layer. The segment of metal capping layer covers and abuts at least a portion of a top surface of the first electrically conductive structure. The method includes forming an opening in the second dielectric layer and the metal capping layer that exposes at least a portion of the first electrically conductive structure and a portion of the dielectric capping layer.

First claim

What is claimed:

1 . A method of fabricating a semiconductor interconnect structure, the method comprising:
providing a semiconductor structure including a first dielectric layer having a first electrically conductive structure embedded therein, a second dielectric layer located above the first dielectric layer, the second dielectric layer and the first dielectric layer having a segment of a dielectric capping layer and a segment of a metal capping layer located therebetween such that the segment of the dielectric capping layer is horizontally planar with the segment of the metal capping layer, the segment of metal capping layer covers and abuts at least a portion of a top surface of the first electrically conductive structure; and forming an opening in the second dielectric layer and the metal capping layer, thereby exposing at least a portion of the first electrically conductive structure and a portion of the dielectric capping layer.

2 . The method of claim 1 , further comprising:
forming a second electrically conductive structure in the opening, such that a first bottom portion of the second electrically conductive structure is located over a portion of the dielectric capping layer, and such that a second bottom portion of the second electrically conductive structure is in electrical contact with the portion of the first electrically conductive structure.

3 . The method of claim 1 , wherein forming the second electrically conductive structure in the opening further comprises:
depositing a first liner material in the opening; removing a portion of the first liner material that is over the portion of the first electrically conductive structure included in the opening; and filling the opening with a second conductive material, such that an electrically conductive connection with low resistivity is formed between the first electrically conductive structure and the second electrically conductive structure, wherein low resistivity is defined as resistivity less than 100 micro-ohm centimeters.

4 . The method of claim 3 , further comprising:
depositing a second liner material in the opening, thereby covering a portion of at least one of the first liner material, the dielectric capping layer, and the first electrically conductive structure, wherein the second liner material is selected for low resistivity and for wettability of the second conductive layer.

5 . The method of claim 4 , wherein the second liner material comprises at least one layer comprising one or more of: Cu, Ru, and Co.

6 . The method of claim 1 , wherein the dielectric capping layer comprises a dielectric material that inhibits metal diffusion between the second electrically conductive structure and the first dielectric layer.

7 . The method of claim 1 , wherein the metal capping layer comprises at least one layer comprising one or more of: Co, Ru, W, Ta, Ti, P, and Rh.

8 . The method of claim 1 , wherein forming the opening in the second dielectric layer and the metal capping layer comprises:
forming the opening in the metal capping layer using a metal etch process that is selective to etching the metal capping layer while minimizing removal of the first conductive material and the dielectric capping layer.

9 . The method of claim 8 , wherein the metal etch process comprises:
a first etchant comprising a dilute nitric acid solution with typical concentrations of 20 to 60 percent volume per volume (% v/v); and a second etchant comprising a mixture of hydrogen peroxide with typical concentrations of 3 to 15 percent weight per weight (% w/w), and a quaternary ammonium compound with typical concentrations of 0.2 to 1.5% w/w.

10 . The method of claim 3 , wherein removing the portion of the first liner material comprises:
removing the portion of the first liner material utilizing a liner material removal process that is selective to removing one or more horizontal portions of the first liner material with minimal removal of one or more vertical portions of the first liner material.

11 . The method of claim 10 , wherein the liner material removal process comprises:
an ion-sputtering process with a gas resource including at least one of: Ar, He, Xe, Ne, Kr, Rn, N2 and H2.

Assignees

• IBM

Inventors

• Murray Conal E
• Yang Chih-Chao

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title