Methods of forming microelectronic smart tags

Patent metadata

Field	Value
Publication number	US-9953501-B2
Application number	US-201715466122-A
Country	US
Kind code	B2
Filing date	Mar 22, 2017
Priority date	Oct 29, 2015
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A method comprises forming a structure, the structure comprising at least one of a wafer, a panel and a roll to roll structure and forming a plurality of integrated circuit chips from the structure. At least a given one of the plurality of integrated circuit chips or a heterogeneous integrated sub-component thereof forms a smart tag comprising a processor, a non-volatile memory, an internal power source, and a transceiver configured for two-way communication with a reader external to the smart tag. The given integrated circuit chip less than 10 cubic millimeters in size.

First claim

The invention claimed is:

1. A method comprising:
forming a structure, the structure comprising at least one of a wafer, a panel and a roll to roll structure;
forming a plurality of integrated circuit chips from the structure;
wherein at least a given one of the plurality of integrated circuit chips or a heterogeneous integrated sub-component thereof forms a smart tag comprising a processor, a non-volatile memory, an internal power source and a transceiver configured for two-way communication with a reader external to the smart tag;
wherein the given integrated circuit chip is less than 10 cubic millimeters in size;
wherein the given integrated circuit chip comprises:
a first silicon die portion comprising at least the processor;
a first dielet formed over the first silicon die portion and comprising at least a portion of the internal power source via one or more capacitors formed therein; and
a first photovoltaic reflector formed over the first dielet, the first photovoltaic reflector comprising a photovoltaic layer comprising at least a portion of the internal power source and a reflector providing at least a portion of the transceiver; and

wherein the first silicon die portion, the first dielet and the first photovoltaic reflector are interconnected via at least one micro controlled-collapse chip-connection interconnect.

2. The method of claim 1 , wherein the structure comprises:
an alignment layer;
a logic layer over the alignment layer, the logic layer providing at least a portion of the processor;
a power layer over the logic layer, the power layer providing at least a portion of the internal power source.

3. The method of claim 2 , wherein the alignment layer comprises a ferromagnetic alignment layer.

4. The method of claim 1 , wherein forming the plurality of integrated circuit chips from the structure comprises singulating the plurality of integrated circuit chips from the structure utilizing deep silicon etching having a kerf width less than 10 micrometers.

5. The method of claim 1 , wherein the structure comprises:
a silicon die comprising the first silicon die portion;
a plurality of dielets including the first dielet formed over the silicon die; and
photovoltaic reflectors including the first photovoltaic reflector formed over the plurality of dielets;
wherein the plurality of integrated circuit chips are formed from the wafer by separating portions of the silicon die, where each portion of the silicon die has at least one of the plurality of dielets formed thereon.

6. The method of claim 5 , wherein the structure comprises a plurality of interconnects formed between the silicon die and the dielets using at least one of micro controlled-collapse chip-connection (C4) interconnects, micro-pillars and one or more other interconnections between layers or within one of the heterogeneous integrated subcomponents of the structure.

7. The method of claim 1 , wherein the given integrated circuit chip is less than 1 cubic millimeter in size.

8. The method of claim 1 , wherein the given integrated circuit chip has a length less than 0.5 millimeters, a width less than 0.5 millimeters and a height less than 0.5 millimeters.

9. The method of claim 1 , wherein the given integrated circuit chip has a length less than 0.05 millimeters, a width less than 0.05 millimeters and a height less than 0.05 millimeters.

10. The method of claim 1 , further comprising connecting an antenna to the smart tag.

11. The method of claim 10 , wherein the antenna is configured to provide two-way communications between the transceiver of the smart tag and a reader.

12. The method of claim 10 , wherein the antenna is configured to provide power to the integrated circuit chip.

13. The method of claim 10 , wherein the antenna is larger than the integrated circuit chip.

14. A method of forming a smart tag comprising:
forming a silicon die comprising at least a processor;
forming a dielet over the silicon die, the dielet comprising at least a portion of an internal power source for the smart tag;
forming a photovoltaic reflector over the dielet, the photovoltaic reflector comprising a photovoltaic layer and a reflector, the photovoltaic layer comprising at least a portion of the internal power source and the reflector comprising at least a portion of a transceiver of the smart tag configured for two-way communication with a reader external to the smart tag; and
forming at least one micro controlled-collapse chip-connection interconnect between the silicon die, the dielet and the photovoltaic reflector.

15. The method of claim 14 , wherein the smart tag comprises an integrated circuit chip less than 10 cubic millimeters in size.

16. The method of claim 14 , wherein the smart tag comprises an integrated circuit chip less than 1 cubic millimeter in size.

17. The method of claim 14 , wherein the smart tag comprises an integrated circuit chip having a length less than 0.5 millimeters, a width less than 0.5 millimeters and a height less than 0.5 millimeters.

18. The method of claim 14 , wherein the smart tag comprises an integrated circuit chip having a length less than 0.05 millimeters, a width less than 0.05 millimeters and a height less than 0.05 millimeters.

19. The method of claim 14 , further comprising forming one or more capacitors in the dielet.

20. The method of claim 19 , wherein one or more of the capacitors comprise deep trench capacitors.

Assignees

• IBM

Inventors

• Andry Paul S
• Denneau Monty Montague
• Knickerbocker John U
• Wisnieff Robert L

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W46/301

  for alignment · CPC title

• H10W44/248

  for antennas · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title