Slope wave generation circuit and digital-to-analog conversion circuit thereof, fingerprint identification system

Patent metadata

Field	Value
Publication number	US-9953203-B2
Application number	US-201615248621-A
Country	US
Kind code	B2
Filing date	Aug 26, 2016
Priority date	Oct 24, 2014
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

The present disclosure, related to the technical field of fingerprint identification, discloses a ramp wave generation circuit, a digital-to-analog conversion circuit, and a fingerprint identification system. The ramp wave generation circuit comprises: an integrating circuit, configured to output a ramp wave signal; a signal regulation circuit, comprising a feedback control loop and a transconductance amplifier connected in series, wherein the feedback control loop monitors the ramp wave signal output by the integrating circuit, and outputs a regulation control signal to the transconductance amplifier, the transconductance amplifier corrects, according to the regulation control signal, a ramp wave signal output by the integrating circuit within a next period; and a voltage generation circuit, configured to respectively output a reference voltage signal to the integrating circuit and the signal regulation circuit.

First claim

What is claimed is:

1. A ramp wave generation circuit, comprising:
an integrating circuit, configured to output a ramp wave signal;
a signal regulation circuit, comprising a feedback control loop and a transconductance amplifier connected in series, wherein the feedback control loop is configured to monitor the ramp wave signal, and output a regulation control signal to the transconductance amplifier, and the transconductance amplifier is configured to correct, according to the regulation control signal, a ramp wave signal output by the integrating circuit within a next period; and
a voltage generation circuit, configured to respectively output a reference voltage signal to the integrating circuit and the signal regulation circuit;
wherein the feedback control loop comprises an error amplifier, wherein a positive input of the error amplifier is connected to a ramp wave signal output of the integrating circuit, a negative input of the error amplifier is connected to the voltage generation circuit, and an output of the error amplifier is connected to the transconductance amplifier.

2. The ramp wave generation circuit according to claim 1 , wherein the integrating circuit comprises a first bilateral switch, a second bilateral switch, a third bilateral switch, a ramp wave signal generation capacitor and a first high-gain operational amplifier; wherein
the first bilateral switch is connected between a negative input and an output of the first high-gain operational amplifier;
one terminal of the ramp wave signal generation capacitor is connected to the negative input of the first high-gain operational amplifier, and the other terminal of the ramp wave signal generation circuit is connected to the output of the first high-gain operational amplifier via the second bilateral switch; and
one terminal of the third bilateral switch is connected to the voltage generation circuit, and the other terminal of the third bilateral switch is connected between the ramp wave signal generation capacitor and the second bilateral switch.

3. The ramp wave generation circuit according to claim 2 , wherein the first bilateral switch, the second bilateral switch and the third bilateral switch are respectively controlled by two paths of phase-reverse and non-overlapped periodic signals.

4. The ramp wave generation circuit according to claim 2 , wherein the transconductance amplifier comprises an error retaining capacitor and an NMOS transistor, wherein a gate of the NMOS transistor is connected to an output of the feedback control loop, one of the remaining two terminals of the NMOS transistor is connected to the ground, and the other of the remaining two terminals is connected to the negative input of the first high-gain operational amplifier of the integrating circuit to provide an error correction current for the integrating circuit.

5. The ramp wave generation circuit according to claim 1 , wherein the voltage generation circuit comprises a second high-gain operational amplifier, a current mirror circuit, a first matching resistor, a second matching resistor and a third matching resistor; wherein
the current mirror circuit is formed by two PMOS transistors that are connected in a current mirror manner, wherein a first connection terminal of the current mirror circuit is connected to an output of the second high-gain operational amplifier, a first connection terminal of the first matching resistor is connected to a positive input of the first high-gain operational amplifier of the integrating circuit, and a second connection terminal of the first matching resistor is connected to a first connection terminal of the second matching resistor and a voltage input terminal of the signal regulation circuit;
a first connection terminal of the third matching resistor is connected to a second connection terminal of the second matching resistor and a first connection terminal of the third bilateral switch of the integrating circuit, and a second connection terminal of the third matching resistor is connected to a second connection terminal of the first matching resistor and is grounded; and
a negative input of the second high-gain operational amplifier is connected to an output of the second high-gain operational amplifier.

6. A fingerprint identification system, comprising a digital-to-analog conversion circuit, wherein the digital-to-analog conversion circuit comprises a ramp wave generation circuit, and the ramp wave generation circuit comprises:
an integrating circuit, configured to output a ramp wave signal;
a signal regulation circuit, comprising a feedback control loop and a transconductance amplifier connected in series, wherein the feedback control loop is configured to monitor the ramp wave signal output by the integrating circuit, and output a regulation control signal to the transconductance amplifier; the transconductance amplifier is configured to correct, according to the regulation control signal, a ramp wave signal output by the integrating circuit within a next period; and
a voltage generation circuit, configured to respectively output a reference voltage signal to the integrating circuit and the signal regulation circuit;
wherein the feedback control loop comprises an error amplifier, wherein a positive input of the error amplifier is connected to a ramp wave signal output of the integrating circuit, a negative input of the error amplifier is connected to the voltage generation circuit, and an output of the error amplifier is connected to the transconductance amplifier.

7. The fingerprint identification system according to claim 6 , wherein the integrating circuit comprises a first bilateral switch, a second bilateral switch, a third bilateral switch, a ramp wave signal generation capacitor and a first high-gain operational amplifier; wherein
the first bilateral switch is connected between a negative input and an output of the first high-gain operational amplifier;
one terminal of the ramp wave signal generation capacitor is connected to the negative input of the first high-gain operational amplifier, and the other terminal of the ramp wave signal generation circuit is connected to the output of the first high-gain operational amplifier via the second bilateral switch; and
one terminal of the third bilateral switch is connected to the voltage generation circuit, and the other terminal of the third bilateral switch is connected between the ramp wave signal generation capacitor and the second bilateral switch.

8. The fingerprint identification system according to claim 7 , wherein the first bilateral switch, the second bilateral switch and the third bilateral switch are respectively controlled by two paths of phase-reverse and non-overlapped periodic signals.

9. The fingerprint identification system according to claim 7 , wherein the transconductance amplifier comprises an error retaining capacitor and an NMOS transistor, wherein a gate of the NMOS transistor is connected to an output of the feedback control loop, one of the remaining two terminals of the NMOS transistor is connected to the ground, and the other of the remaining two terminals is connected to the negative input of the first high-gain operational amplifier of the integrating circuit to provide an error correction current for the integrating circuit.

10. The fingerprint system according to claim 6 , wherein the voltage generation circuit comprises a second high-gain operational amplifier, a current mirror circuit, a first matching resistor, a second matching resistor and a third matching resistor; wherein
the current mirror circuit is formed by two PMOS transistors that are connected in a current mirror manner, wherein a first connection terminal of the current mirror

Assignees

• Shenzhen Huiding Technology Co
• Shenzhen Goodix Tech Co Ltd

Inventors

• Chen Songtao

Classifications

• H03K4/08 Primary

  having sawtooth shape · CPC title

• G06V40/1306

  non-optical, e.g. ultrasonic or capacitive sensing · CPC title

• G06V10/28

  Quantising the image, e.g. histogram thresholding for discrimination between background and foreground patterns · CPC title

• H03M1/56

  Input signal compared with linear ramp · CPC title

• G06K9/38

  Physics · mapped topic