Ramp generator circuit and solid-state imaging device

Patent metadata

Field	Value
Publication number	US-9374070-B2
Application number	US-201414552446-A
Country	US
Kind code	B2
Filing date	Nov 24, 2014
Priority date	May 29, 2012
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

A ramp generator circuit includes: a reference signal generator circuit which generates a ramp waveform having a slope obtained by multiplication using a power of 2 according to a value of a higher order bit of a gain control signal; a clock control circuit which selectively outputs 2^m kinds of fractional-N clocks according to one of 2^m (natural number) areas obtained by dividing a code range represented by a lower order bit, when a negative gain is set; and a variable gain circuit which sets a ramp waveform according to the value of the gain control signal, and sets a ramp signal amplitude in each area so that a period ratio between ramp driving clocks for adjacent areas and a ratio between an amplitude of a ramp signal when the standard gain is set and a largest amplitude of a ramp signal are equal.

First claim

The invention claimed is:

1. A ramp generator circuit comprising:
a reference signal generator circuit which generates a ramp waveform by outputting a step voltage signal in synchronization with a ramp driving clock having a frequency obtained by multiplying an input clock frequency by a predetermined power of 2 according to a value of a higher order bit of a gain control signal, the step voltage signal having a voltage variable by a fixed amount per unit time ranging from a predetermined start voltage to a predetermined end voltage;
a clock control circuit which:
(i) when a value of a gain control signal indicates a negative gain smaller than a standard gain, associates, one to one, fractional-N clocks as input clocks of the reference signal generator circuit with areas, and selectively outputs, as one of the input clocks of the reference signal generator circuit, one of the fractional-N clocks which is used in an associated one of the areas, the fractional-N clocks comprising 2^m kinds of fractional-N clocks obtained by performing fractional-N frequency division on a frequency of a base clock according to 1/{2^(m+1)−n} (an integer satisfying 0≦n<2^m) and being associated with the areas in an ascending order of frequencies, the areas being obtained by dividing a code range of 2^m (an integer satisfying m>0) represented by a lower order bit of the gain control signal and being associated with the input clocks in an ascending order of differences from a value of a gain control signal at a time when the standard gain is set; and
(ii) when the value of the gain control signal indicates a positive gain larger than or equal to the standard gain, selectively outputs, as one of the input clocks of the reference signal generator circuit, a lowest-frequency fractional-N clock among the 2^m kinds of fractional-N clocks;
a standard voltage control circuit which outputs a standard voltage controlled to have a magnification equal to a period ratio between the one of the input clocks selectively output from the clock control circuit and an input clock of the reference signal generator circuit at the time when the standard gain is set;
a variable gain circuit which:
(i) controls amplitudes of ramp signals exponentially so that amplitude rates each defined by a ratio between a slope of a ramp signal in a case where the value of the gain control signal is a preset value of the standard gain and a slope of a ramp signal in a case where the value of the gain control signal is an arbitrarily set value of a gain become linear with respect to the value of the gain control signal; and
(ii) sets the predetermined start voltage and the predetermined end voltage which define the ramp waveform which is of each of the areas so that (a) a period ratio between ramp driving clocks for adjacent ones of the areas and (b) a ratio between an amplitude of a ramp signal at the time when the standard gain is set and a largest amplitude of a ramp signal in each of the areas are equal to each other, when the value of the gain control signal indicates the negative gain after receiving the standard voltage output from the standard voltage control circuit; and
an attenuator which is connected to a subsequent stage of the reference signal generator circuit, and outputs a ramp signal by attenuating the ramp waveform generated by the reference signal generator circuit.

2. The ramp generator circuit according to claim 1 ,
wherein the attenuator (i) fixedly sets an attenuation ratio to a predetermined value when the value of the gain control signal indicates the negative gain, (ii) sets the attenuation ratio so that an amplification rate of an entire system including the amplification rates becomes linear with respect to the value of the gain control signal by performing variable control on the attenuation ratio when the value of the gain control signal indicates a positive gain larger than or equal to the standard gain, and (iii) outputs the ramp signal by attenuating the ramp waveform generated by the reference signal generator circuit according to the attenuation ratio.

3. The ramp generator circuit according to claim 1 ,
wherein the reference signal generator circuit includes:
a ladder resistor string in which a plurality of unit resistors are connected in series;
switches each of which selects one of voltage division points which are connection points in the ladder resistor string; and
a shift register which causes the switches to switch between open and closed states, and
the shift register:
(i) sequentially causes, starting with one of the switches which is closest to one of both ends of the ladder resistor string, the switches to switch between open and closed states in synchronization with the ramp driving clock, so that voltages generated sequentially at the voltage division points selected by the switches form a ramp waveform;
(ii) includes a plurality of flip-flops and a plurality of selectors arranged alternately in a column, and controls the selectors according to a value of a higher order bit of the gain control signal so that each of the voltage division points which are for a power-of-2 number of flip-flops positioned serially on a per power-of-2 basis among the plurality of flip-flops is switched in synchronization with the ramp driving clock; and
(iii) changes the slope of the ramp waveform on a per power-of-2 basis according to the value of the higher order bit of the gain control signal, by voltages generated by the shift register at the voltage division points for the power-of-2 number of flip-flops.

4. The ramp generator circuit according to claim 2 ,
wherein the attenuation ratio is variably controlled by a power-of-2 ratio according to a value of a higher order bit of the gain control signal, when the value of the gain control signal indicates the positive gain.

5. A solid-state imaging device comprising:
the ramp generator circuit according to claim 1 ;
a pixel array unit in which unit pixels including photo-electric conversion elements are arranged two-dimensionally in rows and columns and column signal lines are provided for the unit pixels on a per column basis in the rows and columns;
a row scanning unit which selectively controls each of the unit pixels of the pixel array unit on a per row basis;
comparators each of which compares (i) an analog signal output from each of the unit pixels in one of the rows selectively controlled by the row scanning unit via a corresponding one of the column signal lines with (ii) the ramp signal that is a reference signal;
counters which count time from a start time of comparison by the comparators to a time at which outputs from the comparators are inverted;
digital memories which are arranged on a per column basis and store values counted by the counters; and
a timing control unit which generates a base clock for generating the ramp signal, a timing signal, and the gain control signal, based on a master clock and control information input from an external system,
wherein the ramp generator circuit generates the ramp signal in response to the base clock and the gain control signal.

Assignees

• Panasonic Ip Man Co Ltd
• Paansonic Intellectual Property Man Co Ltd

Inventors

• Higuchi Masahiro
• Fujinaka Hiroshi
• Ikuma Makoto

Classifications

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N25/618

  for random or high-frequency noise · CPC title

• H10F39/182

  Colour image sensors · CPC title

• H03K4/08

  having sawtooth shape · CPC title

• H04N5/378

  Electricity · mapped topic