Semiconductor device

Patent metadata

Field	Value
Publication number	US-9948283-B2
Application number	US-201715419798-A
Country	US
Kind code	B2
Filing date	Jan 30, 2017
Priority date	Mar 22, 2016
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

When a signal of high amplitude is outputted, a drain-to-source voltage exceeding a withstand voltage may be applied. The semiconductor device according to the present invention includes a level shift circuit that outputs a high amplitude signal from the input of a low amplitude logical signal. The level shift circuit includes a series coupling circuit, a first gate control circuit coupled to a first power supply, a second gate control circuit coupled to a second power supply of a potential higher than the potential of the first power supply, and a potential conversion circuit arranged between the first gate control circuit and the series coupling circuit. The potential conversion circuit supplies a first level potential, which is lower than the potential of the first power supply and higher than the potential of the reference power supply, to a gate of an N-channel MOS transistor of the series coupling circuit.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor chip including a level shift circuit to output a high amplitude signal from an input of a low amplitude logical signal,
wherein the level shift circuit comprises
a series coupling circuit;
a potential generating circuit;
a first gate control circuit coupled to a first power supply;
a second gate control circuit coupled to a second power supply of a potential higher than the potential of the first power supply; and
a first potential conversion circuit arranged between the first gate control circuit and the series coupling circuit,
wherein the series coupling circuit comprises
a first P-channel MOS transistor with a source coupled to the second power supply;
a second P-channel MOS transistor with a source coupled to a drain of the first P-channel MOS transistor;
a first N-channel MOS transistor with a source coupled to a reference power supply;
a second N-channel MOS transistor with a source coupled to a drain of the first N-channel MOS transistor; and
a first output node to which a drain of the second P-channel MOS transistor and a drain of the second N-channel MOS transistor are coupled,
wherein the potential generating circuit generates a first potential that is lower than the potential of the second power supply and higher than the potential of the reference power supply and that is applied to a gate of the second P-channel MOS transistor, a second potential that is lower than the potential of the second power supply and higher than the potential of the reference power supply and that is applied to a gate of the second N-channel MOS transistor, and a third potential that is lower than the potential of the second power supply and higher than the potential of the reference supply,
wherein the first gate control circuit generates a first signal that has the amplitude between the potential of the reference power supply and the potential of the first power supply and that controls a gate of the first N-channel MOS transistor,
wherein the second gate control circuit generates a second signal that has the amplitude between the first potential and the potential of the second power supply and that controls a gate of the first P-channel MOS transistor, and
wherein the first potential conversion circuit supplies a first level potential that is lower than a high level of the first signal and higher than the potential of the reference power supply, to the gate of the first N-channel MOS transistor.

2. The semiconductor device according to claim 1 ,
wherein a substrate of the first P-channel MOS transistor is coupled to the second power supply,
wherein a substrate of the second P-channel MOS transistor is coupled to the drain of the first P-channel MOS transistor,
wherein a substrate of the first N-channel MOS transistor is coupled to the reference power supply, and
wherein a substrate of the second N-channel MOS transistor is coupled to the drain of the first N-channel MOS transistor.

3. The semiconductor device according to claim 1 ,
wherein the first potential conversion circuit supplies a potential higher than the first level potential to the gate of the first N-channel MOS transistor based on a first control signal.

4. The semiconductor device according to claim 3 further comprising:
a second potential conversion circuit arranged between the second gate control circuit and the series coupling circuit,
wherein the second potential conversion circuit supplies a second level potential that is higher than the low level of the second signal and lower than the second power supply potential, to a gate of first P-channel MOS transistor.

5. The semiconductor device according to claim 4 ,
wherein the second potential conversion circuit supplies a potential lower than the second level potential to the gate of the first P-channel MOS transistor based on a second control signal.

6. The semiconductor device according to claim 1 ,
wherein the first potential conversion circuit includes a first transfer gate comprised of a third N-channel MOS transistor with a gate coupled to the first power supply, and a substrate of the third N-channel MOS transistor is coupled to a second output node of the first transfer gate.

7. The semiconductor device according to claim 3 ,
wherein the first potential conversion circuit includes a second transfer gate comprised of a third P-channel MOS transistor with a gate supplied with the first control signal, and a substrate of the third P-channel MOS transistor is coupled to a first input node of the second transfer gate.

8. The semiconductor device according to claim 4 ,
wherein the second potential conversion circuit includes a third transfer gate comprised of a fourth P-channel MOS transistor with a gate coupled to the first power supply, and a substrate of the fourth P-channel MOS transistor is coupled to a second input node of the third transfer gate.

9. The semiconductor device according to claim 5 ,
wherein the second potential conversion circuit includes a fourth transfer gate comprised of a fourth N-channel MOS transistor with a gate supplied with the second control signal, and a substrate of the fourth N-channel MOS transistor is coupled to a third output node of the fourth transfer gate.

10. The semiconductor device according to claim 1 ,
wherein the first gate control circuit comprises
a first inverter circuit to output an inverted signal obtained by inverting an input signal; and
a second inverter circuit to output the first signal obtained by inverting the inverted signal.

11. The semiconductor device according to claim 10 ,
wherein the first inverter circuit comprises
a fifth P-channel MOS transistor with a source coupled to the first power supply;
a fifth N-channel MOS transistor with a source coupled to the reference power supply;
a third input node to which a gate of the fifth P-channel MOS transistor and a gate of the fifth N-channel MOS transistor are coupled; and
a fourth output node to which a drain of the fifth P-channel MOS transistor and a drain of the fifth N-channel MOS transistor are coupled, and
wherein the input signal is applied to the third input node and the inverted signal is applied to the fourth output node.

12. The semiconductor device according to claim 10 ,
wherein the second gate control circuit comprises
a clamping circuit to clamp to the first potential and the second potential;
a latch circuit operating between the second power supply potential and the first potential; and
a latch inverting circuit that operates between the second potential and the reference power supply, and
wherein the second signal is outputted from the fifth output node of the latch circuit.

13. The semiconductor device according to claim 12 ,
wherein the latch circuit is comprised of a sixth and a seventh P-channel MOS transistor with sources both coupled to the second power supply and with gates cross-coupled to the other drains, and in the latch circuit, a drain of the sixth P-channel MOS transistor is coupled to the seventh output node.

14. The semiconductor device according to claim 12 ,
wherein the clamping circuit is comprised of a series coupling circuit of an eighth P-channel MOS transistor and a sixth N-channel MOS transistor with drains coupled mutually, and a series coupling circuit of a ninth P-channel MOS transistor and a seventh N-channel MOS transistor with drains coupled mutually, and in the clamping circuit, a source of the eighth P-channel MOS transistor is coupled to a drain of the sixth P-channel MOS transistor, a source of the ninth P-channel MOS trans

Assignees

• Renesas Electronics Corp

Inventors

• Takayanagi Koji

Classifications

• H03K19/00315

  in field-effect transistor circuits · CPC title

• H03K17/102

  in field-effect transistor switches · CPC title

• H03K19/018557 Primary

  Coupling arrangements; Impedance matching circuits · CPC title

• H03K3/356113 Primary

  using additional transistors in the input circuit · CPC title

• H03K3/356182 Primary

  with additional means for controlling the main nodes · CPC title