Semiconductor structure having a junction field effect transistor and a high voltage transistor and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9947786-B2
Application number	US-201514942527-A
Country	US
Kind code	B2
Filing date	Nov 16, 2015
Priority date	Apr 3, 2015
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

The present examples relate to a junction field effect transistor (JFET) that shares a drain with a high voltage field effect transistor. The present examples are able to control a pinch-off feature of the junction transistor while also maintaining electric features of the high voltage transistor by forming a groove on a lower part of a first conductivity type deep-well region located on a channel region of the junction transistor in a channel width direction.

First claim

What is claimed is:

1. A semiconductor device comprising:
a high voltage transistor and a junction field effect transistor (JFET) formed on a substrate, wherein
the JFET comprises
a first conductivity type deep-well region comprising a diffusion region located on the substrate,
a second conductivity type buried impurity layer located on the first conductivity type deep-well region,
a first conductivity type common drain region located on the first conductivity type deep-well region,
a first conductivity type first source region located on the first conductivity type deep-well region,
a second conductivity type pick-up region formed on the substrate, and
an insulating layer formed on the substrate between the first conductivity type common drain region and the first conductivity type first source region, wherein
the diffusion region has an impurity concentration that is lower than other portions of the first conductivity type deep-well region.

2. The semiconductor device of claim 1 , wherein the high voltage transistor comprises:
a gate electrode located on the substrate; and
a second source region located around the gate electrode, wherein
the first conductivity type common drain region is located a certain distance apart from the gate electrode.

3. The semiconductor device of claim 1 , wherein a groove is located on a lower side of the diffusion region.

4. The semiconductor device of claim 3 , wherein a pinch-off region is located in the diffusion region.

5. The semiconductor device of claim 1 , further comprising:
a first terminal connected to the first conductivity type common drain region;
a second terminal connected to the first conductivity type first source region; and
a third terminal connected to the pick-up region, wherein
the first and second terminals are electrically connected to the first conductivity type deep-well region,
the third terminal is electrically connected to the substrate, and
in response to a first voltage, which is a voltage difference between the first terminal and the third terminal, being or larger than a pinch-off voltage, a depletion region is formed in the first conductivity type deep-well region.

6. The semiconductor device of claim 5 , wherein in response to the first voltage being smaller than the pinch-off voltage, the output voltage of the second terminal is proportionate to the first voltage, and wherein in response to the first voltage being the same or larger than the pinch-off voltage, a voltage of the second terminal becomes a fixed voltage.

7. The semiconductor device of claim 1 , wherein the second conductivity type buried impurity layer is formed to be in contact with a lower side of the insulating layer or formed separately in a vertical direction of a substrate surface.

8. The semiconductor device of claim 1 , wherein the first conductivity type deep-well region comprises a first deep-well region and a second deep-well region, and
the diffusion region is located between the first deep-well region and the second deep-well region and formed by an impurity diffusion of the first deep-well region and the second deep-well region.

9. The semiconductor device of claim 8 , wherein the first deep-well region has a higher doping concentration of an impurity than the second deep-well region and/or is formed to be deeper than the second deep-well region.

10. The semiconductor device of claim 1 , wherein the diffusion region comprises a first deep-well region and a second deep-well region formed by ion injection of a first conductivity type impurity on the substrate using a mask pattern with a predetermined width, wherein the diffusion region is formed through a thermal processing process that diffuses the first conductive type impurity.

11. A semiconductor device comprising:
a first conductivity type deep-well region located on a substrate;
a second conductivity type buried impurity layer located on the first conductivity type deep-well region;
a first conductivity type first drain region and a first source region located on the first conductivity type deep-well region;
a second conductivity type first pick-up region located on the substrate;
an insulating layer located on a surface of the substrate between the first conductivity type first drain region and the first source region; and
a junction field effect transistor (JFET) gate region formed on a part of the first conductivity type deep-well region, formed to be in contact with a lower part of the insulating layer, and formed to pass through the second conductivity type buried impurity layer.

12. The semiconductor device of claim 11 , comprising:
a high voltage transistor located on the first conductivity type deep-well region, wherein
the high voltage transistor comprises
a gate electrode,
a second source region and a second pick-up region located on a side of the gate electrode, and
a second drain region located separated by a certain distance from the gate electrode,
wherein the first drain region and the second drain region are identical.

13. The semiconductor device of claim 12 , wherein the JFET gate region and the second pick-up region are electrically connected.

14. The semiconductor device of claim 11 , further comprising:
a first terminal connected to the first drain region;
a second terminal connected to the first source region; and
a third terminal connected to the pick-up region; wherein
the first and second terminals are electrically connected to the first conductivity type deep-well region,
the third terminal is electrically connected to the substrate, and
in response to a first voltage, which is a voltage difference between the first terminal and the third terminal, being the same or larger than the pinch-off voltage, a depletion region is formed in the first conductivity type deep-well region, and
in response to the first voltage being smaller than the pinch-off voltage, the output voltage of the second terminal is proportional to the first voltage and in response to the first voltage being equal to or larger than a pinch-off voltage, a voltage of the second terminal becomes a fixed voltage.

15. A semiconductor device comprising:
a first conductivity type deep-well region having a first concentration and located on a substrate;
a first conductivity type semiconductor region having a second concentration that is lower in concentration than the first concentration and located in the first conductivity type deep-well region;
a second conductivity type impurity layer that is located on the first conductivity type deep-well region;
a first conductivity type drain region and a source region that are located separately from the semiconductor region; and
a second conductivity type pick-up region located on the substrate, wherein
the second conductivity type impurity layer is in contact with the semiconductor region, and
a pinch-off voltage is generated through the semiconductor region.

16. The semiconductor device of claim 15 , wherein the first conductivity type deep-well region comprises a first deep-well region and a second deep-well region,
the first deep-well region and the second deep-well region are located to be in contact with the semiconductor region, and
wherein the first conductivity type deep-well region is formed by diffusion of a first conductivity type dopant in the first deep-well region and the second deep-well region.

17. The semiconductor device of claim 14 , further comprising a JFET gate region formed to pass through the second conductivity type impurity layer.

18.

Assignees

• Magnachip Semiconductor Ltd

Inventors

• Kim Young Bae
• Kim Kwang Il

Classifications

• H10D64/257

  for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H01L29/0688

  Electricity · mapped topic

• H01L29/7832 Primary

  Electricity · mapped topic

• H01L29/808

  Electricity · mapped topic