Integrated circuit devices including stress proximity effects and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9490177-B2
Application number	US-201213617582-A
Country	US
Kind code	B2
Filing date	Sep 14, 2012
Priority date	Apr 25, 2012
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

An integrated circuit can include first and second FETs of a particular conductivity type on a substrate, wherein a first source/drain region of the first FET is closer to a center of a first channel region of the first FET than a second source/drain region of the second FET is to a center of a second channel region of the second FET.

First claim

What is claimed is:

1. An integrated circuit comprising:
first and second fin field effect transistors (finFETs) of same particular conductivity type on a substrate, wherein a first source/drain of the first finFET that includes electrically active impurities of a first conductivity type throughout the first source/drain is closer to a first gate electrode of the first finFET than a second source/drain of the second finFET that includes electrically active impurities of the same first conductivity type throughout the second source/drain is to a second gate electrode of the second finFET,
wherein a first channel region of the first finFET and a second channel region of the second finFET comprise respective fins that extend from the substrate to protrude from a device isolation layer to provide upper side walls and a top surface of the respective fins positioned between the first and second source/drains, respectively,
wherein the first gate electrode of the first finFET and the second gate electrode of the second finFET each wrap around three sides of the respective one of the first and second channel regions.

2. The circuit of claim 1 wherein a first interface of the first source/drain and the first channel region is closer to the first gate electrode than a second interface of the second source/drain and the second channel region is to the second gate electrode.

3. The circuit of claim 1 wherein the first and second source/drains comprise a particular lattice constant, and wherein the first source/drain applies greater stress to the first channel region than the second source/drain applies to the second channel region.

4. The circuit of claim 3 wherein the first source/drain extends past an outermost lower corner of a gate structure of the first finFET into the first channel region to define an undercut region beneath the first finFET; and
wherein the second source/drain is aligned to a gate structure of the second finFET.

5. The circuit of claim 1 wherein the first and second source/drains comprise first and second raised source/drains, respectively, wherein the first source/drain extends past an outermost lower corner of a gate structure of the first finFET into the first channel region to define a first undercut region beneath the first finFET; and
wherein the second source/drain extends past an outermost lower corner of a gate structure of the second finFET into the second channel region to define a second undercut region beneath the second finFET.

6. The circuit of claim 1 wherein the first and second source/drains comprise different lattice constants than the first and second channel regions.

7. The circuit of claim 1 wherein the first and second source/drains comprise first and second raised source/drains, respectively, wherein the first raised source/drain wraps around an outermost lower corner of a gate structure of the first finFET into the first channel region to define an undercut region beneath the first finFET; and
wherein the second source/drain is formed aligned to a gate structure of the second finFET.

8. The circuit of claim 1 wherein the first and second source/drains comprise first and second raised source/drains, respectively, wherein the first raised source/drain wraps around an outermost lower corner of a gate structure of the first finFET into the first channel region to define a first undercut region beneath the first finFET; and
wherein the second raised source/drain wraps around an outermost lower corner of a gate structure of the second finFET into the second channel region to define a second undercut region beneath the second finFET.

9. The circuit of claim 1 further comprising:
a first spacer including an outer side wall of a gate structure of the first finFET to provide a first thickness; and
a second spacer including an outer side wall of a gate structure of the second finFET to provide a second thickness that is greater than the first thickness.

10. The circuit of claim 9 wherein the first source/drain is formed self-aligned to the first spacer and the second source/drain is formed self-aligned to the second spacer.

11. The circuit of claim 9 wherein a number of layers included in the first spacer is less than a number of layers included in the second spacer.

12. The circuit of claim 11 wherein the first source/drain is formed self-aligned to the first spacer and the second source/drain is formed self-aligned to the second spacer.

13. The circuit of claim 1 wherein the first and second finFETs comprise PMOS finFETs, the first and second channel regions include a first material comprising a first lattice constant and the first and second source/drains include a second material comprising a second lattice constant that is greater than the first lattice constant.

14. The circuit of claim 13 wherein the first material comprises Si and the second material comprises SiGe.

15. The circuit of claim 1 wherein the first and second finFETs comprise NMOS finFETs, the channel regions include a first material comprising a first lattice constant and the source/drains of the first and second finFETs include a second material comprising a second lattice constant that is less than the first lattice constant.

16. The circuit of claim 15 wherein the first material comprises Si and the second material comprises SiC.

17. The circuit of claim 1 wherein at least one of the respective fins comprises a width measured between the upper side walls of about 20 nm or less.

18. The circuit of claim 17 wherein the at least one of the respective fins comprises a side wall image transfer fin.

19. The circuit of claim 1 ,
wherein the first and second gate electrodes each includes a first conductive gate layer in an outer portion of the respective gate electrode and a second conductive gate layer in an inner portion of the respective gate electrode in a recess defined by the first conductive gate layer.

20. The circuit of claim 19 wherein the first and second conductive gate layers comprise first and second metal layers, respectively.

21. The circuit of claim 19 wherein the first metal layers comprise TiN, TaN, TiC, TaC, Si, or SiGe and the second metal layers comprise W and/or Al.

22. The circuit of claim 1 wherein the substrate comprises a bulk silicon or a silicon-on-insulator substrate.

23. An integrated circuit comprising:
a substrate;
a first fin field effect transistor (finFET) of a particular conductivity type on the substrate, including a first gate structure, a first source/drain that includes electrically active impurities of a first conductivity type throughout the first source/drain, and a first channel region, wherein a first interface between the first source/drain and the first channel region is aligned to the first gate structure a first distance from a first gate electrode of the first finFET, and wherein the first gate structure wraps around three sides of the first channel region; and
a second finFET of the particular conductivity type on the substrate, including a second gate structure, a second source/drain that includes electrically active impurities of the same first conductivity type throughout the second source/drain, and a second channel region, wherein the second source/drain wraps around a lower outer corner of the second gate structure to form a second interface between the second source/drain and the second channel region a second distance from a second gate electrode of the second finFET that is less t

Assignees

• Oh Chang-Woo
• Kang Myung-Gil
• Jung Young-Chai
• Samsung Electronics Co Ltd

Inventors

• Oh Chang-Woo
• Kang Myung-Gil
• Jung Young-Chai

Classifications

• H10D84/038 Primary

  using silicon technology, e.g. SiGe · CPC title

• H10D84/0193 Primary

  the components including FinFETs · CPC title

• H10D62/021

  Forming source or drain recesses by etching e.g. recessing by etching and then refilling · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D84/853

  comprising FinFETs · CPC title