Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9793356-B2
Application number	US-201514824057-A
Country	US
Kind code	B2
Filing date	Aug 11, 2015
Priority date	Sep 12, 2014
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

A semiconductor device may have a structure that prevents or reduces an etching amount of certain portions, such as a part of a source/drain region. Adjacent active fins may be merged with a blocking layer extending between adjacent the source/drain region. The blocking layer may be of a material that is relatively high-resistant to the etchant.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate provided with first and second active fins that extend lengthwise in a first direction and are separated in a second direction crossing the first direction by a field insulating layer;
a gate structure which extends in the second direction on the first and second active fins;
a first semiconductor pattern formed on the first active fin and disposed at a first side of the gate structure, the first semiconductor pattern comprising a first semiconductor material;
a second semiconductor pattern formed on the second active fin and disposed at the first side of the gate structure, the second semiconductor pattern comprising the first semiconductor material; and
a third semiconductor pattern conformally formed on and extending between a downwardly facing side of the first semiconductor pattern between the first and second active fins and a downwardly facing side of the second semiconductor pattern between the first and second active fins, the third semiconductor pattern comprising a second semiconductor material different from the first semiconductor material.

2. The semiconductor device of claim 1 , wherein the first semiconductor pattern and the third semiconductor pattern contact each other.

3. The semiconductor device of claim 1 wherein one of the first semiconductor material and the second semiconductor material comprises one of the atomic elements C and Ge which is not present in the other of the first semiconductor material and second semiconductor material.

4. The semiconductor device of claim 1 , wherein the third semiconductor pattern entirely covers a bottom facet of the first semiconductor pattern located between the first and second active fins.

5. The semiconductor device of claim 1 , wherein the third semiconductor pattern entirely covers a downwardly facing facets of the first and second semiconductor patterns located between the first and second active fins.

6. The semiconductor device of claim 1 , wherein the third semiconductor pattern entirely covers the external surface of the first semiconductor pattern and entirely covers the external surface of the second semiconductor pattern.

7. The semiconductor device of claim 1 , wherein the first semiconductor material has a lattice constant smaller than a lattice constant of the second semiconductor material.

8. The semiconductor device of claim 1 , further comprising a void below the third semiconductor pattern between the first semiconductor pattern and second semiconductor pattern and above the field insulating layer.

9. The semiconductor device of claim 1 , further comprising a fourth semiconductor pattern formed in contact with and above the first semiconductor pattern and the second semiconductor pattern.

10. The semiconductor device of claim 9 , wherein the first semiconductor pattern and the fourth semiconductor pattern are different from each other in a concentration of an impurity included in the first semiconductor material.

11. The semiconductor device of claim 1 , wherein the first semiconductor material includes SiP, SiC, and/or SiCP.

12. The semiconductor device of claim 11 , wherein the second semiconductor material includes SiGe.

13. The semiconductor device of claim 11 , further comprising:
tan upper pattern disposed on upper surfaces of the first semiconductor pattern
and upper surfaces of the second semiconductor pattern,
wherein the upper pattern includes the first semiconductor material, and
wherein a concentration of phosphorus included in the upper pattern is higher than a concentration of phosphorus included in the first and second semiconductor patterns.

14. A semiconductor device comprising:
first and second active fins which protrude from a substrate, first and second active fins extending in a first direction and separated in a second direction;
a gate structure which extends in the second direction on the first and second active fins;
a first semiconductor pattern formed on the first active fin;
a second semiconductor pattern formed on the second active fin;
a field insulating layer covering a lower part of both sides of the first and second active fins;
a third semiconductor pattern formed on and extending from the field insulating layer and contacting the first and second semiconductor patterns in a region between the first and second active fins, the third semiconductor pattern including a first semiconductor material; and
a fourth semiconductor pattern formed on the third semiconductor pattern and on the first and second semiconductor patterns and including a second semiconductor material different from the first semiconductor material of the third pattern.

15. The semiconductor device of claim 14 , further comprising a void below the third semiconductor pattern between the first semiconductor pattern and second semiconductor pattern and above the field insulating layer.

16. The semiconductor device of claim 14 , wherein one of the first semiconductor material and the second semiconductor material comprises one of the atomic elements C and Ge which is not present in the other of the first semiconductor material and second semiconductor material.

17. The semiconductor device of claim 14 , wherein the first and second semiconductor patterns include the second semiconductor material.

18. The semiconductor device of claim 17 , wherein a concentration of an impurity included in the fourth semiconductor pattern is higher than a concentration of an impurity included in the first and second semiconductor patterns.

19. A semiconductor device, comprising:
a substrate in which a first region and a second region are defined, the substrate being provided with first and second active fins in the first region and third and fourth active fins in the second region;
a first gate structure on the first and second active fins;
a first semiconductor pattern, formed on the first and second active fins, disposed at least at one side of the first gate structure, and including a first semiconductor material;
a second semiconductor pattern, formed on downwardly facing surfaces of the first semiconductor pattern between the first and second active fins and including a second semiconductor material different from the first semiconductor material;
a second gate structure on the third and fourth active fins; and
a third semiconductor pattern, formed on the third and fourth active fins, disposed at least at one side of the second gate structure, and including the second semiconductor material.

20. The semiconductor device of claim 19 , further comprising a void below the second semiconductor pattern between the first and second active fins.

21. The semiconductor device of claim 19 , wherein one of the first semiconductor material and the second semiconductor material comprises one of the atomic elements C and Ge which is not present in the other of the first semiconductor material and second semiconductor material.

22. The semiconductor device of claim 19 , wherein the first semiconductor material includes an n-type impurity element.

23. The semiconductor device of claim 22 , wherein the second semiconductor material includes germanium and the first semiconductor material comprises SiP, SiC, and/or SiCP.

24. The semiconductor device of claim 19 , wherein the first semiconductor material comprises SiP, SiC, and/or SiCP.

25. The semiconductor device of claim 24 , wher

Assignees

• Yoo Jeong-Ho
• Lee Byeong-Chan
• Noh Hyun-Ho
• Park Yong-Kook
• Koo Bon-Young
• Joe Jin-Yeong
• Samsung Electronics Co Ltd

Inventors

• Yoo Jeong-Ho
• Lee Byeong-Chan
• Noh Hyun-Ho
• Park Yong-Kook
• Koo Bon-Young
• Joe Jin-Yeong

Classifications

• H01L21/845

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic

• H01L27/0924

  Electricity · mapped topic

• H01L29/1608 Primary

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic