Comparator circuit, imaging apparatus using the same, and method of controlling comparator circuit

Patent metadata

Field	Value
Publication number	US-2015138411-A1
Application number	US-201414517794-A
Country	US
Kind code	A1
Filing date	Oct 17, 2014
Priority date	Nov 15, 2013
Publication date	May 21, 2015
Grant date	—

Abstract

An object of the present invention is to provide a comparator which has an input voltage range larger than the case where a conventional offset cancel technique is used, while reducing an offset voltage. A comparator circuit includes: a comparator having an inverting input terminal, a non-inverting input terminal and an output terminal; a first switch having one terminal connected to the inverting input terminal and having the other terminal connected to the output terminal; a first capacitor which has one end connected with the inverting input terminal; a first signal input terminal which is another end of the first capacitor; and a second signal input terminal which selectively inputs either one of a fixed voltage and a comparing signal into the non-inverting input terminal.

First claim

1 . A comparator circuit comprising:
a comparator having an inverting input terminal, a non-inverting input terminal and an output terminal; a first switch having terminals, one terminal of the terminals of the first switch connected to the inverting input terminal, the other terminal of the terminals of the first switch connected to the output terminal; a first capacitor having terminals, one terminal of the terminals of the first capacitor receiving an analog signal, the other terminal of the terminals of the first capacitor being connected to the inverting input terminal and the one terminal of the first switch; a second capacitor having terminals, one terminal of the terminals of the second capacitor being connected to the non-inverting input terminal, the other terminal of the terminals of the second capacitor receiving a comparing signal; and a second switch having terminals, one terminal of the terminals of the second switch being connected to the one terminal of the second capacitor and the non-inverting input terminal, the other terminal of the terminals of the second switch receiving a fixed voltage.

2 . The comparator circuit according to claim 1 , wherein the comparator circuit performs a circuit operation in
a first state such that the first switch is set at a conducting state, to hold an output voltage of the comparator by the first capacitor, and a second state such that the first switch is set at a non-conducting state, and the other terminal of the second switch receives the comparing signal.

3 . The comparator circuit according to claim 1 , wherein
the fixed voltage and the comparing signal are supplied through a common wiring connected to the other terminal of the second switch.

4 . The comparator circuit according to claim 2 , wherein,
in the first state, the second switch is further set at a conducting state, to input the fixed voltage to the one terminal of the second capacitor and the non-inverting input terminal, and, in the second state, the second switch is further set at a non-conducting state, to hold a voltage difference between the one terminal and the other terminal of the second capacitor.

5 . The comparator circuit according to claim 1 , wherein
the comparing signal is a ramp signal of a voltage increasing or decreasing monotonically as a time elapses.

6 . An imaging apparatus comprising:
a plurality of pixels arranged in rows and columns, to output a pixel signal or a reset signal column by column; a readout circuit configured to be input the pixel signal or the reset signal column by column of the pixels, and to output the pixel signal and the reset signal processed; a reference signal generating unit configured to output the fixed voltage or the comparing signal as a reference signal; and a comparator circuit according to claim 1 , wherein the comparator circuit is input signals output from the readout circuit through the first capacitor, as the analog signal, and is input the reference signal from the reference signal generating unit through the second capacitor.

7 . The imaging apparatus according to claim 6 , wherein
the readout circuit further comprises an amplifier configured to amplify or non-amplify selectively the voltage of the pixel signal or the reset signal.

8 . A controlling method of the comparator circuit according to claim 1 , wherein the method comprises:
a first controlling including setting the first switch at the conducting state, and inputting the fixed voltage to the non-inverting input terminal, to hold, by the first capacitor, the output voltage of the comparator; and a second controlling including setting the first switch at the non-conducting state, and inputting the comparing signal to the non-inverting input terminal.

9 . An imaging system comprising:
the imaging apparatus according to claim 6 ; and processing unit for processing a signal from the imaging apparatus.

Assignees

• Canon Kk

Inventors

• Nakamura Kohichi
• Kobayashi Hideo
• Hiyama Hiroki
• Yamazaki Kazuo

Classifications

• H03K5/249 Primary

  using clock signals · CPC title

• H03M1/56

  Input signal compared with linear ramp · CPC title

• H03K5/125

  Discriminating pulses (measuring characteristics of individual pulses G01R29/02; separation of synchronising signals in television systems H04N5/08) · CPC title

• H03M1/1295

  Clamping, i.e. adjusting the DC level of the input signal to a predetermined value · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title