Semiconductor structure having a test structure formed in a group III nitride layer

Patent metadata

Field	Value
Publication number	US-9947600-B2
Application number	US-201715622109-A
Country	US
Kind code	B2
Filing date	Jun 14, 2017
Priority date	May 10, 2016
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

In an embodiment, a semiconductor structure includes a support substrate comprising a surface adapted to support epitaxial growth of a Group III nitride, one or more epitaxial Group III nitride layers arranged on the surface and supporting a plurality of transistor devices assembled upon the support substrate, and a test structure formed in a Group III nitride layer. The test structure includes a plurality of trenches configured to provide an optical diffraction grating when illuminated by UV light. The trenches have a parameter corresponding to a parameter of a feature of the transistor devices.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a support substrate comprising a surface adapted to support epitaxial growth of a Group III nitride;
one or more epitaxial Group III nitride layers arranged on the surface and supporting a plurality of transistor devices assembled upon the support substrate; and
a test structure formed in a Group III nitride layer, the test structure comprising a plurality of trenches configured to provide an optical diffraction grating when illuminated by UV light, the trenches having a parameter corresponding to a parameter of a feature of the transistor devices.

2. The semiconductor structure of claim 1 , wherein the test structure is arranged in a portion of one of a transistor device, a test device and a saw street.

3. The semiconductor structure of claim 1 , wherein the support substrate comprises one of <111> Si, <110> silicon, SiC and sapphire, wherein the semiconductor structure further comprises a buffer structure arranged on the surface of the support structure and a gallium nitride layer arranged on the buffer structure, and wherein the Group III nitride layer including the test structure includes a barrier Al x Ga 1-x N layer arranged on the gallium nitride layer.

4. The semiconductor structure of claim 1 , wherein the parameter is depth and the depth corresponds to a depth of a barrier recess of the transistor devices.

5. The semiconductor structure of claim 1 , wherein the parameter is depth, wherein the Group III nitride layer including the test structure includes a p-doped Group III nitride layer arranged on a Al x Ga 1-x N barrier layer, and wherein the depth corresponds to a height of a mesa including p-doped Group III nitride of the transistor devices.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Heider Franz
• Brunner Bernhard
• Ostermaier Clemens

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/27

  Structural arrangements therefor · CPC title

• H10P14/3416 Primary

  Nitrides · CPC title

• G01B11/0633

  using one or more discrete wavelengths · CPC title

• G01B2210/56

  Measuring geometric parameters of semiconductor structures, e.g. profile, critical dimensions or trench depth · CPC title