Radio communication

Patent metadata

Field	Value
Publication number	US-9942070-B2
Application number	US-201515312148-A
Country	US
Kind code	B2
Filing date	Jun 9, 2015
Priority date	Jun 13, 2014
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A radio transmitter ( 4 ) comprises an encoder ( 5 ) that receives one or more variable message bits, and encodes each message bit that has a first value as a predetermined first binary chip sequence and encodes each message bit that has the opposite value as a predetermined second binary chip sequence. The radio transmitter ( 4 ) transmits data packets, each comprising (i) a predetermined synchronization portion, comprising one or more instances of the first binary chip sequence, and (ii) a variable data portion, comprising one or more encoded message bits output by the encoder. A radio receiver ( 9 ) receives such data packets. It uses the synchronization portion of a received data packet to perform a frequency and/or timing synchronization operation, and then decodes message bits from the data portion of the data packet.

First claim

The invention claimed is:

1. A radio transmitter comprising an encoder configured to receive one or more variable message bits and to encode each message bit that has a first value as a predetermined first binary chip sequence and to encode each message bit that has the opposite value as a predetermined second binary chip sequence,
wherein the radio transmitter is configured to transmit data packets, each comprising (i) a predetermined synchronisation portion, comprising one or more instances of the first binary chip sequence, and (ii) a variable data portion, comprising one or more encoded message bits output by the encoder;
wherein the radio transmitter is configured to transmit the data packets modulated on a radio carrier signal using Gaussian frequency-shift-keying (GFSK), and
wherein the modulation of the first and second binary chip sequences is such that, for each binary chip sequence of the first and second binary chip sequences, the respective phase of the radio carrier signal at the end of the binary chip sequence is the same as the respective phase of the radio carrier signal at the start of the binary chip sequence.

2. The radio transmitter of claim 1 , wherein the GFSK modulation has a modulation index of approximately 0.5.

3. The radio transmitter of claim 1 , wherein one or each of the first and second binary chip sequences has a bit-length that is an even number greater than or equal to four.

4. The radio transmitter of claim 1 , wherein one or each of the first and second binary chip sequences consists of an equal number of zero bits and one bits.

5. The radio transmitter of claim 1 , wherein the second binary chip sequence is identical to the first binary chip sequence except at a first bit position and a last bit position, at which the second binary chip sequence differs from the first binary chip sequence.

6. The radio transmitter of claim 1 , wherein a first bit of the first binary chip sequence differs from a last bit of the first binary chip sequence.

7. The radio transmitter of claim 1 , wherein the first binary chip sequence has maximum autocorrelation performance, over a set of all possible binary sequences having lengths equal to a length of the first binary chip sequence, subject to constraints that the sequences in the set must have an equal number of zero bits and one bits, and that each sequence in the set must have a first bit that differs in value from a last bit of the respective sequence of the set.

8. The radio transmitter of claim 1 , wherein the first binary chip sequence has an autocorrelation quality of less than 0.26, determined as a ratio of a maximum sidelobe amplitude to a zero-lag peak amplitude when the first binary chip sequence is correlated with a pulse train of four sequence-repetitions.

9. The radio transmitter of claim 1 , wherein the first binary chip sequence is a 16-bit sequence selected from the group consisting of: (0 0 0 1 1 0 1 0 1 1 0 0 1 0 1 1), (1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 0), (1 1 1 0 0 1 0 1 0 0 1 1 0 1 0 0), and (0 0 1 0 1 1 0 0 1 0 1 0 0 1 1 1).

10. The radio transmitter of claim 1 , wherein the variable data portions of the data packets follow after the synchronisation portions without any gap.

11. A radio receiver configured to:
receive data packets, each comprising a predetermined synchronisation portion, comprising one or more instances of a predetermined first binary chip sequence, and a variable data portion, comprising one or more encoded message bits, wherein each message bit that has a first value is encoded as the first binary chip sequence and each message bit that has the opposite value is encoded as a predetermined second binary chip sequence, wherein the data packets are modulated on a radio carrier signal using Gaussian frequency-shift-keying (GFSK), and wherein the modulation of the first and second binary chip sequences is such that, for each binary chip sequence of the first and second binary chip sequences, the respective phase of the radio carrier signal at the end of the binary chip sequence is the same as the respective phase of the radio carrier signal at the start of the binary chip sequence;
use the synchronisation portion of a received data packet to perform a frequency or timing synchronisation operation, before decoding the variable data portion of the received data packet; and
decode message bits from the variable data portion of the received data packet.

12. The radio receiver of claim 11 , configured to demodulate the variable data portion of a received data packet using a differential-binary-phase-shift-keying (DBPSK) demodulator.

13. The radio receiver of claim 11 , comprising a correlator, and configured to use the correlator for performing the frequency and/or timing synchronisation operation.

14. The radio receiver of claim 13 , wherein the correlator is a fixed-coefficient correlator.

15. The radio receiver of claim 11 , comprising a correlator that is switchable between two modes: a first mode in which the correlator correlates against the complete first binary chip sequence, and a second mode in which the correlator correlates against a sub-sequence of the first binary chip sequence.

16. The radio receiver of claim 12 , configured to use the correlator in the first mode for processing the synchronisation portion of a received data packet, and to switch the correlator to the second mode for decoding message bits from the variable data portion.

17. The radio receiver of claim 12 , wherein the sub-sequence is defined by bit positions in the first binary chip sequence at which the first and second binary chip sequences have equal values.

18. The radio receiver of claim 15 , wherein the sub-sequence consists of all the bits of the first binary chip sequence except for the first and last bits of the first binary chip sequence.

19. The radio receiver of claim 13 , wherein the correlator is configured to output amplitude information and wherein the radio receiver is configured to use the amplitude information to perform symbol timing synchronisation.

20. The radio receiver of claim 13 , wherein the correlator is configured to output phase information and wherein the radio receiver is configured to use the phase information to perform an initial frequency synchronisation.

21. The radio receiver of claim 13 , configured to use phase information from the correlator to perform on-going frequency drift tracking, and to apply appropriate adjustment or compensation if the frequency of a received signal drifts.

22. The radio receiver of claim 13 , configured to use the correlator to determine whether a sub-sequence in the variable data portion of a received data packet has an approximately 0 or an approximately π phase change relative to an immediately-preceding occurrence of the sub-sequence in the variable data portion, and to use a signal representative of sub-sequence phase changes from the correlator over the variable data portion to determine the message bits.

23. A radio receiver comprising a fixed-coefficient correlator that is switchable between a first mode in which the correlator is configured to correlate a received signal against a binary chip sequence, and a second mode in which the correlator is configured to correlate a received signal against a sub-sequence from the binary chip sequence, shorter than the binary chip sequence, wherein the correlator is configured, when in the second mode, to output a signal representative of a phase shift between two successive oc

Assignees

• Nordic Semiconductor Asa

Inventors

• Engelien-Lopes David Alexandre
• Wichlund Sverre
• Olsen Eivind
• Corbishley Phil
• Bruset Ola

Classifications

• H04L27/2662

  Symbol synchronisation · CPC title

• H04L27/2017 Primary

  in which the phase changes are non-linear, e.g. generalized and Gaussian minimum shift keying, tamed frequency modulation (H04L27/201 takes precedence) · CPC title

• H04L27/2659

  Coarse or integer frequency offset determination and synchronisation · CPC title

• H04L2027/0046

  Open loops · CPC title

• H04L2027/0065

  Frequency error detectors (H04L2027/0067 takes precedence) · CPC title