Digital system for estimating signal non-energy parameters using a digital phase locked loop

Patent metadata

Field	Value
Publication number	US-9729308-B2
Application number	US-201615385614-A
Country	US
Kind code	B2
Filing date	Dec 20, 2016
Priority date	Jan 26, 2015
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A digital system of measuring parameters of the signal (phase, frequency and frequency derivative) received in additive mixture with Gaussian noise. The system is based on the use of variables of a PLL for calculating preliminary estimates of parameters and calculating the corrections for these estimates when there is a spurt frequency caused by a receiver motion with a jerk. A jerk is determined if the low pass filtered signal of the discriminator exceeds a certain threshold. The jerk-correction decreases the dynamic errors. Another embodiment includes a tracking filter for obtaining preliminary estimates of parameters to reduce the fluctuation errors. Estimates are taken from the tracking filter when there is no jerk and from the block of jerk-corrections when there is a jerk.

First claim

What is claimed is:

1. A system for estimating parameters of an input signal, the system comprising:
a) a digital phase locked loop that includes:
i) a phase discriminator that determines a phase difference z i d between the input signal and reference signals from a Numerically Controlled Oscillator (NCO); and
ii) a loop filter with a control period T c that generates a phase control signal φ i r for the NCO and a frequency control signal f i r for the NCO; and

b) a block for calculation of full phase φ i NCO according to
φ i NCO =φ i−1 NCO +φ i r ·Δ φ NCO +f i−1 r ·Δ ω NCO ·T c ,

where Δ φ NCO is a phase step size in the NCO, and Δ ω NCO is a frequency step size in the NCO;
c) a low-pass filter inputting the phase difference ,z i d and outputting z i A ;
d) a block that uses the full phase φ i NCO for generation of:
a preliminary estimate {circumflex over (φ)} i c,E for a phase of the input signal, and
a preliminary estimate {circumflex over (ω)} i c,E for a frequency of the input signal;

e) a threshold unit outputting a true/false value J i based on the output z i A ; and
f) a block for jerk-corrections of the preliminary estimates that generates an estimate {circumflex over (φ)} i c for a phase of the input signal, and an estimate {circumflex over (ω)} i c for the frequency of the input signal, based on J i , z i A , {circumflex over (φ)} i c,E and {circumflex over (ω)} i c,E .

2. The system of claim 1 , wherein the loop filter operates based on:

s
i
γ

=

s

i
-
1

γ

+

γ
·

z
i
d

,

s
i
β

=

s

i
-
1

β

+

s
i
γ

+

β
·

z
i
d

,

φ
i
r

=

round
⁢

⁢

(

α
·

z
i
d

/

Δ
φ
NCO

)

,

f
i
r

=

round
⁢

⁢

(

s
i
β

/

Δ
ω
NCO

/

T
c

)

,

}

,

where α, β, γ are constants,
s i β corresponds to the frequency of the input signal,
s i γ corresponds to a rate of change of the frequency of the input signal, and
round (·) is numerical rounding.

3. The system of claim 2 , wherein the block in (d) that generates the preliminary estimate {circumflex over (φ)} i c,E and the preliminary estimate {circumflex over (ω)} i c,E also uses s i γ .

4. The system of claim 3 , wherein the block in (d) that uses φ i NCO and s i γ also generates a preliminary estimate {dot over ({circumflex over (ω)})} i c,E of a derivative of the frequency of the input signal.

5. The system of claim 4 , wherein the block for jerk-corrections also generates an estimate {dot over ({circumflex over (ω)})} i c for the derivative of the frequency of the input signal based on

Assignees

• Topcon Positioning Systems Inc

Inventors

• Zhodzishsky Mark I
• Prasolov Victor A
• Zhodzishsky Dmitry M

Classifications

• H04L7/0331 Primary

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H04L27/2017

  in which the phase changes are non-linear, e.g. generalized and Gaussian minimum shift keying, tamed frequency modulation (H04L27/201 takes precedence) · CPC title

• H03L7/08

  Details of the phase-locked loop · CPC title

• H04L7/0332

  with an integrator-detector · CPC title

• H03L7/085 Primary

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title