Fully differential operational amplifier

Patent metadata

Field	Value
Publication number	US-9941850-B1
Application number	US-201615284150-A
Country	US
Kind code	B1
Filing date	Oct 3, 2016
Priority date	Oct 3, 2016
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A fully differential operational amplifier is provided. The amplifier has input nodes and includes a differential input stage for receiving input signals over the input nodes and providing output signals on first and second intermediary nodes. The amplifier includes a fully differential amplification stage having positive and negative inputs coupled to the first and second intermediary nodes, respectively. The amplifier includes a first compensation transistor having conduction terminals coupled to the first intermediary node and a first node, and a control terminal coupled to a negative output of the fully differential amplification stage. The amplifier includes a second compensation transistor having conduction terminals coupled to the second intermediary node and a second node, and a control terminal coupled to a positive output of the fully differential amplification stage. The amplifier includes positive and negative output stages for providing amplifier outputs and feeding the outputs back to the amplifier.

First claim

The invention claimed is:

1. A fully differential operational amplifier, comprising:
first and second amplifier input nodes;
first and second amplifier output nodes;
a differential input stage having a first input coupled to the first amplifier input node, a second input coupled to the second amplifier input node, a first output coupled to a first intermediary node and a second output coupled to a second intermediary node;
a level shifting and amplification stage having first and second outputs, the level shifting and amplification stage including:
a fully differential amplification stage having a positive input coupled to the first intermediary node, a negative input coupled to the second intermediary node, a negative output, and a positive output;
a first compensation transistor having a first conduction terminal coupled to the first intermediary node, a second conduction terminal coupled to the first output of the level shifting and amplification stage, and a control terminal coupled to the negative output of the fully differential amplification stage; and
a second compensation transistor having a first conduction terminal coupled to the second intermediary node, a second conduction terminal coupled to the second output of the level shifting and amplification stage, and a control terminal coupled to the positive output of the fully differential amplification stage;

a positive output stage having an input coupled to first output of the level shifting and amplification stage, and an output coupled to the first amplifier output node, the positive output stage including a first compensating capacitor coupled between the first amplifier output node and the positive input of the fully differential amplification stage at the first intermediary node; and
a negative output stage having an input coupled to the first output of the level shifting and amplification stage and an output coupled to the second amplifier output node, the negative output stage including a second compensating capacitor coupled between the second amplifier output node and the negative input of the fully differential amplification stage at the second intermediary node.

2. The fully differential operational amplifier of claim 1 , wherein the fully differential amplification stage includes:
a level shifting stage having, as inputs, the positive input and the negative input of the fully differential amplification stage, the level shifting stage having a first output, and a second output;
an amplification stage having a first input coupled to the first output of the level shifting stage, and a second input coupled to the second output of the level shifting stage, the amplification stage having, as outputs, the negative output and the positive output of the fully differential amplification stage.

3. The fully differential operational amplifier of claim 2 , wherein the level shifting stage includes:
a first level shifting transistor having a first conduction terminal coupled to a power supply node, a control terminal coupled to the first intermediary node, and a second conduction terminal; and
a second level shifting transistor having a first conduction terminal coupled to the second conduction terminal of the first level shifting transistor, a control terminal for receiving a bias voltage, and a second conduction terminal coupled to a ground node.

4. The fully differential operational amplifier of claim 3 , wherein the amplification stage includes:
a first amplification transistor having a first conduction terminal for receiving a current, a control terminal coupled to the second conduction terminal of the first level shifting transistor, and a second conduction terminal coupled to the control terminal of the first compensation transistor; and
a second amplification transistor having a first conduction terminal and a control terminal that are both coupled to the control terminal of the first compensation transistor, and a second conduction terminal coupled to a ground node.

5. The fully differential operational amplifier of claim 2 , wherein the level shifting stage includes:
a third level shifting transistor having a first conduction terminal coupled to a power supply node, a control terminal coupled to the second intermediary node, and a second conduction terminal; and
a fourth level shifting transistor having a first conduction terminal coupled to the second conduction terminal of the third level shifting transistor, a control terminal for receiving a bias voltage, and a second conduction terminal coupled to a ground node.

6. The fully differential operational amplifier of claim 5 , wherein the amplification stage includes:
a third amplification transistor having a first conduction terminal for receiving a current, a control terminal coupled to the second conduction terminal of the third level shifting transistor, and a second conduction terminal coupled to the control terminal of the second compensation transistor; and
a fourth amplification transistor having a first conduction terminal and a control terminal that are both coupled to the control terminal of the second compensation transistor, and a second conduction terminal coupled to a ground node.

7. The fully differential operational amplifier of claim 1 , wherein the positive output stage includes:
a first current source transistor having a first conduction terminal coupled to a voltage source node, a control terminal for receiving a common mode feedback voltage, and a second conduction terminal coupled to the first amplifier output node;
a first voltage gain transistor having a first conduction terminal coupled to the first amplifier output node, a control terminal coupled to the negative output of the fully differential amplification stage, and a second conduction terminal coupled to a ground node.

8. The fully differential operational amplifier of claim 1 , wherein the negative output stage includes:
a second current source transistor having a first conduction terminal coupled to a voltage source node, a control terminal for receiving a common mode feedback voltage, and a second conduction terminal coupled to the second amplifier output node;
a second voltage gain transistor having a first conduction terminal coupled to the second amplifier output node, a control terminal coupled to the positive output of the fully differential amplification stage, and a second conduction terminal coupled to a ground node.

9. The fully differential operational amplifier of claim 1 , comprising a bias stage having a first input coupled to the second output of the level shifting and amplification stage, a second input coupled to the first output of the level shifting and amplification stage, a first output coupled to the first amplifier output node, and a second output coupled to the second amplifier output node.

10. The fully differential operational amplifier of claim 9 , wherein the bias stage includes:
a first biasing transistor having a first conduction terminal coupled to a voltage supply node, a second conduction terminal coupled to the first amplifier output node, and a control terminal;
a second biasing transistor having a first conduction terminal coupled to a voltage supply node, and a second conduction terminal and a control terminal that are both coupled to the control terminal of the first biasing transistor; and
a third biasing transistor having a first conduction terminal coupled to the second conduction terminal of the second biasing transistor, a second conduction terminal coupled to a ground node, and a control terminal coupled to the second output of the level shifting and amplification stage.

11. The fully differential operational amplifier of

Assignees

• St Microelectronics Srl

Inventors

• GIUFFREDI Luca
• Boni Andrea
• Ronchi Marco

Classifications

• H03F2200/72

  the amplifier stage being a common gate configuration MOSFET · CPC title

• H03F1/342

  in field-effect transistor amplifiers · CPC title

• H03F3/45632 Primary

  in differential amplifiers with FET transistors as the active amplifying circuit (H03F3/4578 takes precedence) · CPC title

• H03F1/26 Primary

  Modifications of amplifiers to reduce influence of noise generated by amplifying elements · CPC title

• H03F2200/555

  A voltage generating circuit being realised for biasing different circuit elements · CPC title