Device for generating a vector-modulated output signal and method for generating a vector-modulated output signal

Patent metadata

Field	Value
Publication number	US-9444666-B2
Application number	US-201514942336-A
Country	US
Kind code	B2
Filing date	Nov 16, 2015
Priority date	Mar 20, 2012
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A device for generating a vector-modulated output signal based on a baseband signal having an in-phase component and a quadrature component, a first LO signal for the in-phase component of the baseband signal and a second LO signal for the quadrature component of the baseband signal comprises a baseband combination circuit, which is configured to combine the in-phase component and the quadrature component in order to obtain a plurality of combined IQ signals. Furthermore, the device includes a plurality of mixer cells for generating the vector-modulated output signal, based on the combined IQ signals, the first LO signal and the second LO signal.

First claim

The invention claimed is:

1. A device for generating a vector-modulated output signal based on a baseband signal having an in-phase component and a quadrature component, comprising:
a clock generation circuit configured to generate a plurality of clock signals that each have a duty cycle of less than 50%, and wherein at every instant a maximum of one of the clock signals from the plurality of clock signals is active;
a baseband combination circuit configured to combine the in-phase component and the quadrature component to obtain a plurality of combined IQ signals; and
a plurality of mixer cells configured to generate the vector-modulated output signal based the combined IQ signals, and the plurality of clock signals.

2. The device according to claim 1 ,
wherein the baseband signal comprises a differential baseband signal comprising a differential in-phase component and a differential quadrature component; and
wherein the baseband combination circuit is configured to add subcomponents of the differential in-phase component and subcomponents of the differential quadrature component to obtain the plurality of combined IQ signals.

3. The device according to claim 2 ,
wherein the differential in-phase component has a first subcomponent and a second subcomponent and the differential quadrature component has a first subcomponent and a second subcomponent; and
wherein the baseband combination circuit is configured to:
add the first subcomponent of the differential in-phase component and the first subcomponent of the differential quadrature component in the context of a first addition in order to obtain a first combined IQ signal;
add the second subcomponent of the differential in-phase component and the second subcomponent of the differential quadrature component in the context of a second addition in order to obtain a second combined IQ signal;
add the second subcomponent of the differential in-phase component and the first subcomponent of the differential quadrature component in the context of a third addition in order to obtain a third combined IQ signal; and
add the first subcomponent of the differential in-phase component and the second subcomponent of the differential quadrature component in the context of a fourth addition in order to obtain a fourth combined IQ signal.

4. The device according to claim 1 , wherein each of the combined IQ signals has a plurality of single-bit signals, wherein a single-bit signal of a combined IQ signal forms or predefines a drive signal for one mixer cell from the plurality of mixer cells.

5. The device according to claim 4 , wherein at least one first mixer cell from the plurality of mixer cells is configured to receive at least one drive signal for each of the combined IQ signals.

6. The device according to claim 5 , wherein the first mixer cell is configured to receive a plurality of clock signals based on the first LO signal and the second LO signal and logically combine each of the received drive signals at least with one of the clock signals in order to obtain a current source drive signal for a current source of the mixer cell.

7. The device according to claim 6 , wherein the first mixer cell is configured to impress a first current at a first output terminal of the mixer cell in response to a first state of the current source drive signal, and to impress no current at the first output terminal of the mixer cell in response to a second state of the current source drive signal.

8. The device according to claim 7 , wherein the first mixer cell is configured to combine each received drive signal with another of the received clock signals in order furthermore to obtain a further current source drive signal for the current source, to impress a second current at a second output terminal of the mixer cell in response to a first state of the further current source drive signal and impress no current at the second output terminal in response to a second state of the further current source drive signal.

9. The device according to claim 1 , wherein the clock combination circuit is configured to logically combine the first LO signal with the second LO signal such that the clock signals each have a duty cycle of 25% within a tolerance range of ±10% of a period of one of the clock signals.

10. The device according to claim 1 ,
wherein the first LO signal comprises a first differential LO signal having a first subcomponent and a second subcomponent, and the second LO signal comprises a second differential LO signal having a first subcomponent and a second subcomponent; and
wherein the device further comprises a clock combination circuit configured to:
logically combine the first subcomponent of the first LO signal with the first subcomponent of the second LO signal in order to obtain a first clock signal;
logically combine the second subcomponent of the first LO signal with the second subcomponent of the second LO signal in order to obtain a second clock signal;
logically combine the first subcomponent of the first LO signal with the second subcomponent of the second LO signal in order to obtain a third clock signal; and
logically combine the second subcomponent of the first LO signal with the first subcomponent of the second LO signal in order to obtain a fourth clock signal.

11. The device according to claim 10 ,
wherein the clock combination circuit is configured to subject at least the first subcomponent of the first LO signal and the first subcomponent of the second LO signal to a logical AND combination or to a logical NOR combination to obtain the first clock signal.

12. The device according to claim 1 , further comprising a decoder configured to apply the plurality of clock signals to each of the plurality of mixer cells.

13. The device according to claim 1 , wherein the mixer cells are configured to generate the vector-modulated output signal as a differential vector-modulated output signal having a first subcomponent and a second subcomponent;
wherein the mixer cells are configured to provide the differential vector-modulated output signal such that the first subcomponent thereof is based on a superposition of a plurality of first currents of the mixer cells and the second subcomponent thereof is based on a superposition of second currents of the mixer cells; and
wherein the baseband combination circuit is configured to combine the in-phase component and the quadrature component such that, apart from changeover instants, at every instant one mixer cell from the plurality of mixer cells provides maximally either a first current or a second current.

14. The device according to claim 1 , wherein the baseband combination circuit is configured to:
obtain the first combined IQ signal based on a first logical combination of single-bit signals resulting from the first addition with single-bit signals resulting from the second addition;
obtain the second combined IQ signal based on a second logical combination of the single-bit signals resulting from the first addition with the single-bit signals resulting from the second addition;
obtain the third combined IQ signal base on a third logical combination of single-bit signals resulting from the third addition with single-bit signals resulting from the fourth addition; and
obtain the fourth combined IQ signal based on a fourth logical combination of single-bit signals resulting from the third addition with single-bit signals resulting from the fourth addition.

15. The device according to claim 14 , wherein the baseband combination circuit is configured to carry out the logical combinations of the single-bit signals re

Assignees

• Intel Deutschland Gmbh

Inventors

• Simon Martin
• Geltinger Hans

Classifications

• H04B1/0475

  with means for limiting noise, interference or distortion (H04B1/0483 takes precedence) · CPC title

• H04B1/30

  for homodyne or synchrodyne receivers (demodulator circuits H03D1/22) · CPC title

• H04L27/20 Primary

  Modulator circuits; Transmitter circuits · CPC title

• H04L25/0282

  Provision for current-mode coupling · CPC title

• H04L27/00

  Modulated-carrier systems · CPC title