Three-D power converter in three distinct strata

Patent metadata

Field	Value
Publication number	US-9941788-B2
Application number	US-201715584513-A
Country	US
Kind code	B2
Filing date	May 2, 2017
Priority date	Feb 12, 2014
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A switching power supply in an integrated circuit, an integrated circuit comprising a switching power supply, and a method of assembling a switching power supply in an integrated circuit are disclosed. In one embodiment, the invention provides a three-dimensional switching power supply in an integrated circuit comprising a device layer. The switching power supply comprises three distinct strata arranged in series with the device layer, the three distinct strata including a switching layer including switching circuits, a capacitor layer including banks of capacitors, and an inductor layer including inductors. This switching power supply further comprises a multitude of connectors electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer. The switching circuits, the capacitors and the inductors form a switching power supply for supplying power to the device layer.

First claim

The invention claimed is:

1. A three-dimensional switching power supply in an integrated circuit stack comprising a device layer, the switching power supply comprising:
three distinct strata arranged in series with the device layer, the three distinct strata including
a switching layer including active CMOS switching circuits and through-silicon-vias,
a capacitor layer including a component substrate and capacitors integrated into said component substrate, and
an inductor layer including a substrate and film magnetic inductors; and

a multitude of connectors electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer; and wherein:
the switching circuits, the capacitors and the inductors form a plurality of switching power supplies, and the switching power supplies apply different voltages to different areas of the device layer.

2. The three-dimensional switching power supply according to claim 1 , wherein the film magnetic inductors of the inductor layer are formed in a first surface of the substrate of the inductor layer.

3. The three-dimensional switching power supply according to claim 1 , wherein the film magnetic inductors of the inductor layer are formed inside the substrate of the inductor layer.

4. The three-dimensional switching power supply according to claim 1 , wherein the capacitor layer includes through-silicon-vias.

5. The three-dimensional switching power supply according to claim 4 , wherein the through-silicon-vias of the capacitor layer are filled with an electrical conductor.

6. The three-dimensional switching power supply according to claim 1 , wherein the inductor layer includes through-silicon-vias.

7. The three-dimensional switching power supply according to claim 6 , wherein the through-silicon-vias of the inductor layer are filled with an electrical conductor.

8. The three-dimensional switching power supply according to claim 1 , wherein the magnetic inductors of the inductor layer have copper coils formed in a first surface of the substrate of the inductor layer.

9. The three-dimensional switching power supply according to claim 1 , wherein the magnetic inductors of the inductor layer have copper coils formed inside the substrate of the inductor layer.

10. The three-dimensional switching power supply according to claim 1 , wherein each of the strata has a thickness in a range from about 0.002 inches to 0.050 inches.

11. An integrated circuit comprising:
a device layer;
a switching power supply comprising three distinct strata arranged in series with the device layer, the three distinct strata including
a switching layer including active CMOS switching circuits and through-silicon-vias,
a capacitor layer including a component substrate and capacitors integrated into said component substrate, and
an inductor layer including a substrate and film magnetic inductors; and

a multitude of connectors electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer; and wherein:
the switching circuits, the capacitors and the inductors form a plurality of switching power supplies, and the switching power supplies apply different voltages to different areas of the device layer.

12. The integrated circuit according to claim 11 , wherein the film magnetic inductors of the inductor layer are formed in a first surface of the substrate of the inductor layer.

13. The integrated circuit according to claim 11 , wherein the film magnetic inductors of the inductor layer are formed inside the substrate of the inductor layer.

14. The integrated circuit according to claim 11 , wherein the capacitor layer includes through-silicon-vias.

15. The integrated circuit according to claim 14 , wherein the through-silicon-vias of the capacitor layer are filled with an electrical conductor.

16. A method of assembling a switching power supply in an integrated circuit, the switching power supply including three distinct strata including a switching layer, a capacitor layer, and an inductor layer, the integrated circuit including a device layer, the method comprising:
forming the switching layer with active CMOS switching circuits and through-silicon-vias;
forming the capacitor layer with a component substrate and capacitors integrated into said component substrate;
forming the inductor layer with a substrate and film magnetic inductors;
arranging the three distinct strata of the switching power supply in series with the device layer; and
electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer to form a plurality of switching power supplies, each of the switching power supplies applying different voltages to different areas of the device layer.

17. The method according to claim 16 , wherein the film magnetic inductors of the inductor layer are formed in a first surface of the substrate of the inductor layer.

18. The method according to claim 16 , wherein the film magnetic inductors of the inductor layer are formed inside the substrate of the inductor layer.

19. The method according to claim 16 , wherein the capacitor layer includes through-silicon-vias.

20. The method according to claim 19 , wherein the through-silicon-vias of the capacitor layer are filled with an electrical conductor.

Assignees

• IBM

Inventors

• Andry Paul S
• Chang Leland
• Colgan Evan G
• Knickerbocker John U
• Webb Bucknell C
• Wisnieff Robert

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title