Semiconductor device

Patent metadata

Field	Value
Publication number	US-9356054-B2
Application number	US-201414578919-A
Country	US
Kind code	B2
Filing date	Dec 22, 2014
Priority date	Dec 27, 2013
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A semiconductor device that is suitable for miniaturization is provided. Alternatively, a highly reliable semiconductor device is provided. A semiconductor device including a capacitor and a transistor is provided. In the semiconductor device, the transistor includes a semiconductor layer, the semiconductor layer is positioned over the capacitor, and the capacitor includes a first electrode that is electrically connected to the transistor.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a first transistor;
a capacitor over the first transistor; and
a second transistor over the capacitor, the second transistor overlapping with at least part of the capacitor,
wherein the second transistor includes an oxide semiconductor layer,
wherein the capacitor includes an electrode which is electrically connected to the second transistor,
wherein the oxide semiconductor layer includes an opening, and
wherein the electrode is in contact with the oxide semiconductor layer in the opening.

2. The semiconductor device according to claim 1 , wherein the first transistor includes single crystal silicon.

3. The semiconductor device according to claim 1 ,
wherein the second transistor includes a first conductive layer and a second conductive layer which are in contact with the oxide semiconductor layer,
wherein the first conductive layer includes the opening, and
wherein the electrode is in contact with the first conductive layer in the opening.

4. A semiconductor device comprising:
a first transistor;
a capacitor over the first transistor; and
a second transistor over the capacitor,
wherein the capacitor includes n insulating films and k conductive layers,
wherein n is a natural number and k is a natural number of 2 or more,
wherein each of the n insulating films is between at least two conductive layers of the k conductive layers,
wherein the second transistor includes an oxide semiconductor layer,
wherein the capacitor includes an electrode which is electrically connected to one of a source and a drain of the second transistor,
wherein the oxide semiconductor layer includes an opening, and
wherein the electrode is in contact with the oxide semiconductor layer in the opening.

5. The semiconductor device according to claim 4 , wherein the first transistor includes single crystal silicon.

6. The semiconductor device according to claim 4 ,
wherein the second transistor includes a first conductive layer and a second conductive layer which are in contact with the oxide semiconductor layer,
wherein the first conductive layer includes the opening, and
wherein the electrode is in contact with the first conductive layer in the opening.

7. The semiconductor device according to claim 4 , wherein the n insulating films have a function of blocking at least one of hydrogen, water, and oxygen.

8. The semiconductor device according to claim 4 , wherein the n insulating films include at least one of silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride.

9. The semiconductor device according to claim 4 , wherein the capacitor and the second transistor overlap each other.

10. A semiconductor device comprising:
a first transistor;
a capacitor over the first transistor; and
a second transistor over the capacitor,
wherein the capacitor includes m conductive layers and n insulating films,
wherein m is a natural number of 3 or more, and n is a natural number,
wherein a first insulating film of the n insulating films is between a first conductive layer and a second conductive layer of the m conductive layers,
wherein a second insulating film of the n insulating films is between the second conductive layer and a third conductive layer of the m conductive layers,
wherein the first conductive layer is electrically connected to the third conductive layer and the second transistor,
wherein the third conductive layer is electrically connected to the second transistor by a plug,
wherein a semiconductor layer of the second transistor includes an opening, and
wherein the plug is in contact with the semiconductor layer in the opening.

11. The semiconductor device according to claim 10 , wherein the first transistor includes single crystal silicon.

12. The semiconductor device according to claim 10 , wherein the second transistor includes an oxide semiconductor layer.

13. The semiconductor device according to claim 10 ,
wherein the second transistor includes a source or drain electrode which is in contact with a semiconductor layer of the second transistor,
wherein the source or drain electrode includes the opening, and
wherein the plug is in contact with the source or drain electrode in the opening.

14. The semiconductor device according to claim 10 , wherein the n insulating films have a function of blocking at least one of hydrogen, water, and oxygen.

15. The semiconductor device according to claim 10 , wherein the n insulating films include at least one of silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride.

16. The semiconductor device according to claim 10 , wherein the capacitor and the second transistor overlap each other.

Assignees

• Semiconductor Energy Lab

Inventors

• Miyairi Hidekazu
• Yamazaki Shunpei

Classifications

• H10D30/6744

  Monocrystalline silicon · CPC title

• H10D88/00 Primary

  Three-dimensional [3D] integrated devices · CPC title

• H10D30/6704

  having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title