Method of forming a capacitor structure and capacitor structure

Patent metadata

Field	Value
Publication number	US-9941348-B2
Application number	US-201615142332-A
Country	US
Kind code	B2
Filing date	Apr 29, 2016
Priority date	Apr 29, 2016
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

The present disclosure provides a method of forming a capacitor structure and a capacitor structure. A semiconductor-on-insulator substrate is provided comprising a semiconductor layer, a buried insulating material layer and a semiconductor substrate material. A shallow trench isolation structure defining a first active region on the SOI substrate is formed, the first active region having a plurality of trenches formed therein. Within each trench, the semiconductor substrate material is exposed on inner sidewalls and a bottom face. A layer of insulating material covering the exposed semiconductor substrate material is formed, and an electrode material is deposited on the layer of insulating material in the first active region.

First claim

What is claimed:

1. A method of forming a capacitor structure, comprising:
providing a semiconductor-on-insulator (SOI) substrate, said SOI substrate comprising a semiconductor layer, a buried insulating material layer and a semiconductor substrate material;
forming a plurality of trenches in said SOI substrate, said semiconductor substrate material being exposed on inner sidewalls and a bottom face of each trench of said plurality of trenches;
forming a masking pattern covering a subset of said plurality of trenches;
with said masking pattern in place, forming an insulating material in first and second trenches adjacent each end of said subset not covered by said masking pattern to define isolation structures in said first and second trenches and a first active region including said subset of said plurality of trenches, said masking pattern preventing said insulating material from being formed in said subset of said plurality of trenches;
forming a layer of insulating material over said first active region, said layer of insulating material covering said exposed semiconductor substrate material;
depositing an electrode material on said layer of insulating material in said first active region and in said plurality of trenches; and
forming a contact structure coupled to said electrode material, wherein said electrode material is contiguous in said plurality of trenches after forming said contact structure.

2. The method of claim 1 , wherein forming said layer of insulating material comprises only partially filling each of said plurality of trenches.

3. The method of claim 1 , further comprising implanting dopants into said semiconductor substrate material after forming said plurality of trenches and before forming said layer of insulating material.

4. The method of claim 1 , wherein forming said isolation structure comprises forming deep trenches into said SOI substrate, said deep trenches laterally delimiting said first active region against one or more adjacent active regions.

5. The method of claim 4 , wherein said semiconductor substrate material is at least partially exposed in a second active region being comprised of said one or more adjacent active regions.

6. The method of claim 5 , further comprising forming a contact over said second active region, said contact being electrically coupled to said exposed semiconductor substrate material in said second active region.

7. The method of claim 5 , further comprising implanting dopants into said semiconductor substrate material in said first and second active regions after forming said plurality of trenched and before forming said layer of insulating material.

8. The method of claim 1 , wherein said depositing of said electrode material comprises depositing a material comprising one of polysilicon, amorphous silicon, a metal, and a metal alloy.

9. The method of claim 1 , wherein depositing said electrode material comprises depositing a silicon material on said layer of insulating material, the method further comprising forming a silicide region on said silicon material.

10. The method of claim 9 , further comprising forming a contact over said first active region, said contact being electrically coupled to said silicide region.

11. The method of claim 1 , wherein first portions of said buried insulating material layer remain on said semiconductor substrate material between said plurality of trenches after forming said plurality of trenches.

12. The method of claim 11 , wherein second portions of said semiconductor layer remain above said first portions after forming said plurality of trenches, and the method further comprises removing said second portions prior to depositing said electrode material.

13. The method of claim 11 , wherein said first portions remain on said semiconductor substrate material between said plurality of trenches after depositing said electrode material.

14. A method of forming a capacitor structure, comprising:
providing a semiconductor-on-insulator (SOI) substrate, said SOI substrate comprising a semiconductor layer, a buried insulating material layer and a semiconductor substrate material;
forming an isolation structure that defines a first active region in said SOI substrate;
forming a plurality of trenches in said first active region, said semiconductor substrate material being exposed on inner sidewalls and a bottom face of each trench of said plurality of trenches, wherein first portions of said buried insulating material layer having exposed uppermost surfaces remain on said semiconductor substrate material between said plurality of trenches after forming said plurality of trenches;
forming a layer of insulating material over said first active region and directly on said exposed uppermost surfaces of said buried insulating material layer, said layer of insulating material covering said exposed semiconductor substrate material;
depositing an electrode material on said layer of insulating material in said first active region and in said plurality of trenches; and
forming a contact structure coupled to said electrode material, wherein said electrode material is contiguous in said plurality of trenches after forming said contact structure.

15. The method of claim 14 , wherein forming said layer of insulating material comprises only partially filling each of said plurality of trenches.

16. The method of claim 14 , further comprising implanting dopants into said semiconductor substrate material after forming said plurality of trenches and before forming said layer of insulating material.

17. The method of claim 14 , wherein said semiconductor substrate material is at least partially exposed in a second active region being comprised of one or more adjacent active regions.

18. The method of claim 17 , further comprising forming a contact over said second active region, said contact being electrically coupled to said exposed semiconductor substrate material in said second active region.

19. The method of claim 17 , further comprising implanting dopants into said semiconductor substrate material in said first and second active regions after forming the plurality of trenches and before forming said layer of insulating material.

20. The method of claim 14 , wherein depositing said electrode material comprises depositing a silicon material on said layer of insulating material, the method further comprising:
forming a silicide region on said silicon material; and
forming a contact over said first active region, said contact being electrically coupled to said silicide region.

Assignees

• Globalfoundries Inc

Inventors

• Yan Ran
• Chang Ming-Cheng
• Richter Ralf

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title