Sinusoidal shaped capacitor architecture in oxide

Patent metadata

Field	Value
Publication number	US-10756164-B2
Application number	US-201715474043-A
Country	US
Kind code	B2
Filing date	Mar 30, 2017
Priority date	Mar 30, 2017
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places an oxide layer on top of a metal layer. A photoresist layer is formed on top of the oxide layer and etched with repeating spacing. One of a variety of lithography techniques is used to alter the distance between the spacings. The process etches trenches into areas of the oxide layer unprotected by the photoresist layer and strips the photoresist layer. The top and bottom corners of the trenches are rounded. The process deposits a bottom metal, a dielectric, and a top metal on the oxide layer both on areas with the trenches and on areas without the trenches. The process completes the metal insulator metal capacitor with metal nodes contacting each of the top plate and the bottom plate.

First claim

What is claimed is:

1. A semiconductor device fabrication process comprising:
forming an oxide layer on top of a first metal layer;
forming a photoresist layer on top of the oxide layer;
patterning the photoresist layer;
etching trenches into the oxide layer unprotected by the photoresist layer, wherein the trenches occur at a plurality of approximately equally spaced locations;
stripping the photoresist layer;
depositing a combination of layers comprising a bottom metal layer, a dielectric layer and a top metal layer in the trenches to form a metal-insulator-metal (MIM) capacitor with an oscillating pattern; and
etching the top metal layer and the dielectric in a first location where there are no trenches.

2. The semiconductor device fabrication process as recited in claim 1 , wherein the process further comprises rounding top and bottom corners of the trenches prior to depositing the combination of layers.

3. The semiconductor device fabrication process as recited in claim 2 , wherein the rounding comprises adjusting parameters used for a plasma etching process on the oxide layer within the trenches.

4. The semiconductor device fabrication process as recited in claim 2 , wherein the rounding comprises relatively high temperature oxidation steps on the oxide layer within the trenches.

5. The semiconductor device fabrication process as recited in claim 1 , wherein the process further comprises placing a tetraethyl orthosilicate (TEOS) film along top surfaces of the oxide layer and the trenches and then removed.

6. The semiconductor device fabrication process as recited in claim 1 , wherein the process further comprises placing a first via at the first location creating contact with the bottom metal layer.

7. The semiconductor device fabrication process as recited in claim 6 , wherein the process further comprises:
placing a second via at a second location where there are no trenches creating contact with the top metal layer; and
placing a second metal layer over each of the first via and the second via creating nodes for the MIM capacitor.

Assignees

• Advanced Micro Devices Inc

Inventors

• Schultz Richard T

Classifications

• H10P14/6322

  Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

• H10P76/204

  of organic photoresist masks · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title