Oscillating capacitor architecture in polysilicon for improved capacitance

Patent metadata

Field	Value
Publication number	US-10608076-B2
Application number	US-201715466643-A
Country	US
Kind code	B2
Filing date	Mar 22, 2017
Priority date	Mar 22, 2017
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places a polysilicon layer on top of an oxide layer which is on top of a metal layer. The process etches trenches into areas of the polysilicon layer where the repeated trenches determine a frequency of an oscillating wave structure to be formed later. The top and bottom corners of the trenches are rounded. The process deposits a bottom metal, a dielectric, and a top metal on the polysilicon layer both on areas with the trenches and on areas without the trenches. A series of a barrier metal and a second polysilicon layer is deposited on the oscillating structure. The process completes the MIM capacitor with metal nodes contacting each of the top metal and the bottom metal of the oscillating structure.

First claim

What is claimed is:

1. A semiconductor device fabrication process comprising:
forming a first oxide layer on top of a signal metal layer used for signal interconnects, wherein:
the first oxide layer has a first thickness if a polysilicon layer is used below but not above a metal-insulator-metal (MIM) capacitor; and
the first thickness is based on locating the MIM capacitor closer to the signal metal layer than a given metal layer deposited later to create nodes for the MIM capacitor;

depositing a polysilicon layer on top of the first oxide layer;
forming a photoresist layer on top of the polysilicon layer;
etching the photoresist layer at a plurality of approximately equally spaced locations;
etching trenches into the polysilicon layer unprotected by the photoresist layer, wherein the trenches occur at the plurality of approximately equally spaced locations;
stripping the photoresist layer;
depositing a series of layers on the polysilicon layer to form a metal-insulator-metal capacitor with an oscillating pattern, the series of layers comprising a bottom metal layer, a dielectric layer, and a top metal layer.

2. The semiconductor device fabrication process as recited in claim 1 , wherein the process further comprises forming the first oxide layer on top of the signal metal layer, wherein:
the first oxide layer has a second thickness if a polysilicon layer is used both below and above the MIM capacitor; and
the second thickness is based on locating the MIM capacitor closer to the given metal layer than the signal metal layer.

3. The semiconductor device fabrication process as recited in claim 2 , wherein the process further comprises depositing an additional polysilicon layer, a barrier metal layer and a second oxide layer with a third thickness on the top metal layer if a polysilicon layer is used both below and above a metal-insulator-metal capacitor, wherein the third thickness is based on locating the MIM capacitor closer to the top of the second oxide layer than the signal metal layer.

4. The semiconductor device fabrication process as recited in claim 3 , wherein the process further comprises depositing the second oxide layer with a fourth thickness on the top metal layer with no additional polysilicon layer and no barrier metal layer if a polysilicon layer is used below but not above the metal-insulator-metal capacitor, wherein the fourth thickness is based on locating the MIM capacitor closer to the signal metal layer than the top of the second oxide layer.

5. The semiconductor device fabrication process as recited in claim 4 , wherein the process further comprises etching each layer above the bottom metal layer in a first location where there is no oscillating pattern, wherein the first location is to be used for a first via making contact with the bottom metal layer.

6. The semiconductor device fabrication process as recited in claim 4 , wherein the process further comprises:
placing a second via at a second location where there is an oscillating pattern if a polysilicon layer is used both below and above a metal-insulator-metal capacitor, wherein the second via makes contact with the top metal layer through the barrier metal layer and the additional polysilicon layer; and
placing the second via at a third location where there is no oscillating pattern if a polysilicon layer is used below but not above the metal-insulator-metal capacitor, wherein the second via makes contact with the top metal layer through no intermediate layers.

7. The semiconductor device fabrication process as recited in claim 1 , wherein the process further comprises rounding top and bottom corners of the trenches prior to depositing the series of layers, wherein the rounding comprises performing one or more cycles of relatively high temperature oxidation of the polysilicon layer and oxidation removal.

8. The semiconductor device fabrication process as recited in claim 6 , wherein the process further comprises:
growing an additional oxide layer on the oscillating pattern; and
etching trenches for vias in the additional oxide layer.

9. A semiconductor device comprising:
a signal metal layer used for signal interconnects;
a first oxide layer on top of a signal metal layer used for signal interconnects, wherein:
the first oxide layer has a first thickness if a polysilicon layer is used below but not above a metal-insulator-metal (MIM) capacitor; and
the first thickness is based on locating the MIM capacitor closer to the signal metal layer than a given metal layer deposited later to create nodes for the MIM capacitor;

a polysilicon layer on top of the first oxide layer; and
a series of layers on the polysilicon layer, the series of layers comprising a bottom metal layer, a dielectric layer, and a top metal layer, wherein the polysilicon layer comprises areas with trenches to form a metal-insulator-metal capacitor with an oscillating pattern repeating at a given frequency equal to a frequency of an occurrence of the trenches in the polysilicon layer.

10. The semiconductor device as recited in claim 9 , further comprising the first oxide layer on top of the signal metal layer, wherein:
the first oxide layer has a second thickness if a polysilicon layer is used both below and above the MIM capacitor; and
the second thickness is based on locating the MIM capacitor closer to the given metal layer than the signal metal layer.

11. The semiconductor device as recited in claim 10 , further comprising an additional polysilicon layer, a barrier metal layer and a second oxide layer with a third thickness on the top metal layer if a polysilicon layer is used both below and above a metal-insulator-metal capacitor, wherein the third thickness is based on locating the MIM capacitor closer to the top of the second oxide layer than the signal metal layer.

12. The semiconductor device as recited in claim 11 , further comprising the second oxide layer with a fourth thickness on the top metal layer with no additional polysilicon layer and no barrier metal layer if a polysilicon layer is used below but not above the metal-insulator-metal capacitor, wherein the fourth thickness is based on locating the MIM capacitor closer to the signal metal layer than the top of the second oxide layer.

13. The semiconductor device as recited in claim 12 , further comprising a first via creating contact with the bottom metal layer at a first location where the oscillating pattern is interrupted by a non-oscillating pattern.

14. The semiconductor device as recited in claim 12 , further comprising:
a second via at a second location where there is an oscillating pattern if a polysilicon layer is used both below and above a metal-insulator-metal capacitor creating contact with the top metal layer through the barrier metal layer and the additional polysilicon layer; and
the second via at a third location where there is no oscillating pattern if a polysilicon layer is used below but not above the metal-insulator-metal capacitor, wherein the second via makes contact with the top metal layer through no intermediate layers.

15. The semiconductor device as recited in claim 9 , wherein the signal metal layer is on top of an inter-level dielectric used to insulate metal layers used for interconnects.

16. A non-transitory computer readable storage medium storing program instructions, wherein the program instructions for performing a semiconductor fabrication process are executable by a processor to:
form a first oxide layer on top of a signal metal layer used for signal interconnects, wherein:
the first oxide layer has a first thickness if a

Assignees

• Advanced Micro Devices Inc

Inventors

• Schultz Richard T

Classifications

• H01L21/32134

  Electricity · mapped topic

• H01L21/32136

  Electricity · mapped topic

• H01L28/75

  Electricity · mapped topic

• H01L23/5223

  Electricity · mapped topic

• H01L28/84

  Electricity · mapped topic