Method and apparatus for placing a gate contact inside an active region of a semiconductor

Patent metadata

Field	Value
Publication number	US-9941278-B2
Application number	US-201615202764-A
Country	US
Kind code	B2
Filing date	Jul 6, 2016
Priority date	Jul 6, 2016
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the core. The liner is etched to the level of the TS. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core at a shelf portion of the CB trench. The core is etched to extend the CB trench to a bottom at the gate metal. The shelf portion having a larger area than the bottom. The CB trench is metalized to form a CB contact.

First claim

What is claimed is:

1. A method comprising:
providing a structure having a FinFET disposed in an Rx region, the FinFET including a channel disposed between a pair of source/drain (S/D) regions and a gate (CB) disposed over the channel, the gate including gate metal disposed between gate spacers;
forming a cap over the gate, the cap having an outer liner disposed around an inner core;
forming trench silicide (TS) layers on opposing sides of the gate over the S/D regions;
recessing the TS layers to a level above a level of the gate and below a level of the inner core;
etching the outer liner down to a level proximate the level of the TS layers;
disposing an oxide layer over the structure;
patterning a CB trench into the oxide layer to expose the inner core at a shelf portion of the CB trench, the CB trench located within the Rx region;
etching the inner core to further extend the CB trench to a trench bottom and to expose the gate metal, the shelf portion of the CB trench having a larger area than the trench bottom; and
metallizing the CB trench to form a CB contact electrically connected to the gate metal.

2. The method of claim 1 wherein the cap outer liner has a first material composition and the cap inner core has a second material composition different from the first material composition.

3. The method of claim 2 wherein the first material and second material are nitrides.

4. The method of claim 2 wherein the second material is one of SiBCN and SiCO.

5. The method of claim 1 wherein the shelf portion of the CB trench is located a sufficient distance from any TS layers to substantially prevent electrical shorting between the CB contact and the TS layers within the Rx region.

6. The method of claim 1 comprising recessing the TS layers to a level that is within a range of 25 to 50 percent of the level of the inner core.

7. The method of claim 1 comprising recessing the TS layers within a range of 15 to 30 nm below the level of the inner core.

8. The method of claim 1 comprising disposing a pair of source/drain (CA) contacts for the FinFET within oxide layer, the CA contacts electrically connecting to the TS layers overlaying the S/D regions of the FinFET, the CA contacts located a sufficient distance away from the CB contact in a direction parallel to the gate to substantially prevent electrical shorting between the CB contact and the CA contacts.

9. The method of claim 8 comprising:
patterning a pair of CA trenches into the oxide layer to expose the TS layers over the S/D regions of the FinFET; and
metallizing the CA trenches to form the CA contacts electrically connected to the TS layers.

10. The method of claim 1 comprising:
disposing a dielectric layer on opposing sides of the gate prior to forming the cap;
recessing the gate below a level of the dielectric layer;
disposing a liner layer over the structure, the liner layer having a first material composition;
disposing a core layer over the liner layer, the core layer having a second material composition different from the first material composition;
polishing the core layer and liner layer down to the level of the dielectric layer to form the outer liner and inner core of the cap;
removing of the dielectric layer to form TS trenches; and
forming the TS layer within the TS trenches.

11. A semiconductor structure comprising:
a FinFET disposed in an Rx region, the FinFET including a channel disposed between a pair of source/drain (S/D) regions and a gate disposed over the channel, the gate including gate metal disposed between gate spacers;
a cap including a cap liner disposed over the gate and a cap core disposed on the cap liner, the cap core extending upwards from the cap liner;
trench silicide (TS) layers disposed on opposing sides of the gate over the S/D regions, the TS layers having a level above a level of the gate and below a level of the cap core;
an oxide layer disposed over the structure;
a CB trench disposed within the oxide layer and over the Rx region, the CB trench extending down to a trench shelf portion located at substantially the level of the cap core and further extending from the shelf portion to a trench bottom, the trench bottom including the gate metal, the shelf portion of the CB trench having a larger area than an area of the trench bottom; and
a CB contact disposed within the CB trench and electrically connected to the gate metal.

12. The semiconductor structure of claim 11 wherein the cap liner has a first material composition and the cap core has a second material composition different from the first material composition.

13. The semiconductor structure of claim 12 wherein the first material and second material are nitrides.

14. The semiconductor structure of claim 12 wherein the second material is one of SiBCN and SiCO.

15. The semiconductor structure of claim 11 wherein the shelf portion of the CB trench is located a sufficient distance from any TS layers to substantially prevent electrical shorting between the CB contact and the TS layers within the Rx region.

16. The semiconductor structure of claim 11 comprising the TS layers having a level that is within a range of 25 to 50 percent of the level of the cap core.

17. The semiconductor structure of claim 11 comprising the TS layers having a level that is within a range of 15 to 30 nm below the level of the cap core.

18. The semiconductor structure of claim 11 comprising a pair of source/drain (CA) contacts for the FinFET being disposed within oxide layer, the CA contacts electrically connecting to the TS layers overlaying the S/D regions of the FinFET, the CA contacts located a sufficient distance away from the CB contact in a direction parallel to the gate to substantially prevent electrical shorting between the CB contact and the CA contacts.

19. The semiconductor structure of claim 11 comprising the shelf portion of the CB trench having an area that is more than 50% larger than the area of the trench bottom.

20. The semiconductor structure of claim 11 comprising:
the Rx region including a plurality of fins extending perpendicular to the gate;
a plurality of FinFETs disposed in the fins, each FinFET including a channel disposed between a pair of S/D regions, wherein the gate is disposed over the channels of each FinFET; and
the TS layers disposed on opposing sides of the gate over the S/D regions of each FinFET.

Assignees

• Globalfoundries Inc

Inventors

• Labonte Andre
• Xie Ruilong
• Zhang Xunyuan

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P50/283

  by chemical means · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title