Fully silicided linerless middle-of-line (MOL) contact

Patent metadata

Field	Value
Publication number	US-9634113-B2
Application number	US-201514967736-A
Country	US
Kind code	B2
Filing date	Dec 14, 2015
Priority date	Sep 17, 2015
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A method of making a semiconductor device includes forming a source/drain region on a substrate; disposing a gate stack on the substrate and adjacent to the source/drain region, the gate stack including a gate spacer along a sidewall of the gate stack; disposing an inter-level dielectric (ILD) layer on the source/drain region and the gate stack; removing a portion of the ILD layer on the source/drain region to form a source/drain contact pattern; filling the source/drain contact pattern with a layer of silicon material, the layer of silicon material being in contact with the source/drain region and in contact with the gate spacer; depositing a metallic layer over the first layer of silicon material; and performing a silicidation process to form a source/drain contact including a silicide.

First claim

What is claimed is:

1. A method of making a semiconductor device, the method comprising:
forming a source/drain region on a substrate;
disposing a gate stack on the substrate and adjacent to the source/drain region, the gate stack comprising a gate spacer along a sidewall of the gate stack;
disposing an inter-level dielectric (ILD) layer on the source/drain region and the gate stack;
removing a portion of the ILD layer on the source/drain region to form a source/drain contact pattern;
filling the source/drain contact pattern with a layer of silicon material, the layer of silicon material being in contact with the source/drain region and in contact with the gate spacer;
depositing a metallic layer over the layer of silicon material; and
performing a silicidation process to form a source/drain contact comprising a silicide;
wherein filling the source/drain contact pattern with the silicide further comprises depositing another silicon layer onto the metallic layer and depositing another a metallic layer onto the another silicon layer.

2. The method of claim 1 , wherein the silicidation process includes a low temperature annealing process.

3. The method of claim 1 , wherein the first metallic layer comprises a refractory metal.

4. The method of claim 1 , wherein the source/drain contact consists essentially of the silicide.

5. The method of claim 1 , wherein performing the silicidation process comprises performing a thermal annealing process at a temperature in a range from about 300 to about 600° C.

6. The method of claim 1 , further comprising pre-cleaning the source/drain contact pattern after removing a portion of the ILD layer.

Assignees

• IBM

Inventors

• Rubin Joshua M
• Yamashita Tenko

Classifications

• H10P70/234

  the processing being the formation of vias or contact holes · CPC title

• H10P14/44

  Physical vapour deposition [PVD] · CPC title

• H10D64/0113

  the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10W20/4451

  Semiconductor materials, e.g. polysilicon · CPC title

• H10W20/0698

  Local interconnections · CPC title