Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device

Patent metadata

Field	Value
Publication number	US-9941196-B2
Application number	US-201615130904-A
Country	US
Kind code	B2
Filing date	Apr 15, 2016
Priority date	Nov 29, 2010
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate having a first surface and a second surface opposite to the first surface, the second surface defining a redistribution trench, the substrate having a via hole extending therethrough;
a through via disposed in the via hole, the through via including a via hole insulating layer, a barrier layer and a conductive connector sequentially formed therein;
an insulation layer pattern formed on the second surface of the semiconductor substrate, the insulation layer pattern defining an opening that partially exposes a top surface of the conductive connector; and
a redistribution layer disposed in the redistribution trench and electrically connected to the through via, wherein the insulation layer pattern covers an interface region between the second surface of the substrate and a top surface of the via hole insulating layer,
wherein the top surface of the via hole insulating layer is substantially coplanar with a top surface of the conductive connector, and
wherein a top surface of the conductive connector is lower than a top surface of the insulation layer pattern.

2. The device of claim 1 , wherein the top surface of the via hole insulating layer is substantially coplanar with a bottommost portion of the second surface.

3. The device of claim 1 , wherein a sidewall of the insulation layer pattern is positioned on the top surface of the via hole insulating layer.

4. A semiconductor package comprising:
a package substrate; and a first semiconductor device provided on the package substrate, wherein the first semiconductor device comprises:
a semiconductor substrate having a first surface, and a second surface opposite to the first surface, the second surface defining a redistribution trench, the semiconductor substrate having a via hole extending therethrough;
a first through via disposed in the via hole, the first through via including a via hole insulating layer, a barrier layer, and a conductive connector sequentially formed therein;
an insulation layer pattern formed on the second surface of the substrate, the insulating layer pattern defining an opening that partially exposes a region of a top surface of the conductive connector; and
a redistribution layer disposed in the redistribution trench and electrically connected to the first through via, wherein the insulation layer pattern covers an interface region between the second surface of the substrate and a top surface of the via hole insulating layer,
wherein a width of the redistribution trench is wider than a width of the via hole in cross-section, and
wherein a top surface of the conductive connector is lower than a top surface of the insulation layer pattern.

5. The semiconductor package of claim 4 , wherein the package substrate further comprises a circuit pattern, and the first through via is electrically connected to the circuit pattern.

6. The semiconductor package of claim 4 , further comprising a second semiconductor device overlying the redistribution layer of the first semiconductor device.

7. The semiconductor package of claim 6 , wherein the second semiconductor device includes a second through via, and wherein the second through via does not overlap with the first through via.

8. The semiconductor package of claim 7 , wherein the second semiconductor device includes a connection terminal coupled to the second through via, and wherein the connection terminal is coupled to the redistribution layer.

9. The semiconductor package of claim 8 , further comprising a protective layer overlying the redistribution layer having an opening part exposing a region of the redistribution layer such that the connection terminal can be mounted there on.

10. The semiconductor device of claim 4 , wherein at least a portion of the insulation layer pattern is formed on a bottom surface of the redistribution trench and below the redistribution layer.

11. A semiconductor device comprising:
a semiconductor substrate having a first surface and a second surface opposite to the first surface, the second surface defining a redistribution trench, the substrate having a via hole extending therethrough;
a through via disposed in the via hole, the through via including a via hole insulating layer, a barrier layer and a conductive connector sequentially formed therein;
an insulation layer pattern formed on the second surface of the substrate, the insulation layer pattern defining an opening that partially exposes a top surface of the conductive connector; and
a redistribution layer disposed in the redistribution trench and electrically connected to the through via, wherein the insulation layer pattern covers an interface region between the second surface of the substrate and a top surface of the via hole insulating layer,
wherein a width of the redistribution trench wider than a width of the via hole in cross-section,
wherein the top surface of the via hole insulating layer is substantially coplanar with a top surface of the conductive connector, and
wherein a top surface of the conductive connector is lower than a top surface of the insulation layer pattern and a top surface of the conductive connector is recessed.

12. The device of claim 11 , wherein substantially all of the redistribution trench is disposed above the top surface of the via hole insulating layer in cross-section.

13. The device of claim 11 , wherein the insulation layer pattern extends in a horizontal direction with substantially no extension into the via hole in a vertical direction in cross-section.

14. The device of claim 11 , wherein the insulation layer pattern comprises a single layer.

15. The device of claim 11 , wherein no portion of the insulation layer pattern extends into the via hole in cross-section.

16. The device of claim 11 , wherein at least a portion of the insulation layer pattern is formed on a bottom surface of the redistribution trench and below the redistribution layer.

Assignees

• Lee Ho Jin
• Cho Tae Je
• Jang Dong Hyeon
• Song Ho Geon
• Jeong Se Young
• Kang Un Byoung
• Yoon Min Seung
• Samsung Electronics Co Ltd

Inventors

• Lee Ho-Jin
• Cho Tae-Je
• Jang Dong-Hyeon
• Song Ho-Geon
• Jeong Se-Young
• Kang Un-Byoung
• Yoon Min-Seung

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/9226

  with via interconnections · CPC title

• H10W72/07254

  changes in dispositions · CPC title