Semiconductor device having through electrode and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9041218-B2
Application number	US-201414187357-A
Country	US
Kind code	B2
Filing date	Feb 24, 2014
Priority date	Nov 14, 2007
Publication date	May 26, 2015
Grant date	May 26, 2015

Abstract

A semiconductor device includes a substrate, and a through electrode passing through the substrate. The semiconductor device has a pad region and a through electrode region. A pad covers the pad region, extends into the through electrode region, and delimits an opening in the through electrode region. A through electrode extends through the semiconductor substrate below the hole in the pad in the through region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a first insulating layer disposed on a first side of the substrate;
a second insulating layer disposed on or above the first insulating layer;
a third insulating layer disposed on a second side of the substrate, the second side of the substrate being opposite to the first side of the substrate;
a hole formed through the first insulating layer and the substrate;
a metal layer, a barrier metal and a fourth insulating layer formed within the hole;
an interconnection pattern disposed on the second insulating layer, the interconnection pattern being electrically coupled to the metal layer through a via hole; and
a trench isolation layer formed in the substrate,
wherein the trench isolation layer is not formed directly under the interconnection pattern,
the hole is formed under the interconnection pattern, and
the thickness of the substrate is 100 μm or less.

2. The semiconductor device of claim 1 , wherein the substrate includes a first region and a second region,
the hole passes through the first region of the substrate, and
the trench isolation layer is not formed in the first region of the substrate.

3. The semiconductor device of claim 2 , wherein the second region of the substrate includes the trench isolation layer.

4. The semiconductor device of claim 2 , wherein the interconnection pattern is disposed over the first region.

5. The semiconductor device of claim 1 , wherein the fourth insulating layer encircles the barrier metal, and
the barrier metal encircles the metal layer.

6. The semiconductor device of claim 1 , wherein the trench isolation layer is formed beneath the first side of the semiconductor substrate.

7. A semiconductor device, comprising:
a substrate;
a first insulating layer disposed on a first side of the substrate;
a second insulating layer disposed on or above the first insulating layer;
a third insulating layer disposed on a second side of the substrate, the second side of the substrate being opposite to the first side of the substrate;
a hole formed through the first insulating layer and the substrate;
a metal layer, a barrier metal and a fourth insulating layer formed within the hole;
an interconnection pattern disposed on the second insulating layer, the interconnection pattern being electrically coupled to the metal layer through a via hole and an extension, the via hole being connected to the interconnection pattern, the extension being connected to the via hole; and
a trench isolation layer formed in the substrate,
wherein the hole is not formed under the interconnection pattern,
the thickness of the substrate is 100 μm or less, and
the substrate includes a first region and a second region, the hole passing through the first region, the interconnection pattern being formed over the second region, the trench isolation layer being not formed directly under the interconnection pattern.

8. The semiconductor device of claim 7 , wherein the first region and the second region are adjacent to each other and do not overlap each other.

9. The semiconductor device of claim 7 , wherein the trench isolation layer is formed in the second region of the substrate.

10. The semiconductor device of claim 7 , wherein the fourth insulating layer encircles the barrier metal, and
the barrier metal encircles the metal layer.

11. The semiconductor device of claim 7 , wherein the trench isolation layer is formed under the first side of the semiconductor substrate.

12. A semiconductor device, comprising:
a first chip;
a second chip; and
a conductive electrical connection between the first chip and the second chip,
wherein each of the first chip and the second chip includes:
a substrate, the thickness of the substrate being 100 μm or less;
a first insulating layer disposed on a first side of the substrate;
a second insulating layer disposed on or above the first insulating layer;
a third insulating layer disposed on a second side of the substrate, the second side of the substrate being opposite to the first side of the substrate;
a hole formed through the first insulating layer and the substrate, the hole being formed under the interconnection pattern;
a metal layer, a barrier metal and a fourth insulating layer formed within the hole;
an interconnection pattern disposed on the second insulating layer, the interconnection pattern being electrically coupled to the metal layer through a via hole; and
a trench isolation layer formed in the substrate, the trench isolation layer being not formed directly under the interconnection pattern.

13. The semiconductor device of claim 12 , wherein the interconnection pattern contacts the conductive electrical connection.

14. The semiconductor device of claim 12 , wherein the substrate includes a first region and a second region,
the hole passes through the first region, and
the trench isolation layer is not formed in the first region of the substrate.

15. The semiconductor device of claim 14 , wherein the second region of the substrate includes the trench isolation layer.

16. The semiconductor device of claim 14 , wherein the interconnection pattern is disposed over the first region.

17. The semiconductor device of claim 12 , wherein the substrate includes an active region that includes an integrated circuit.

18. The semiconductor device of claim 12 , wherein the second chip is stacked on the first chip.

19. The semiconductor device of claim 18 , further comprising a resin layer between the first chip and the second chip.

20. The semiconductor device of claim 19 , wherein the resin layer is disposed on the second insulating layer of the first chip, and
the third insulating layer of the second chip is disposed on the resin layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Ki-Tae
• Lee Kang-Wook
• Kim Hyun-Kyoung

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/07251

  characterised by changes in properties of the bump connectors during connecting · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title