Method of manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-9941159-B2
Application number	US-201615255333-A
Country	US
Kind code	B2
Filing date	Sep 2, 2016
Priority date	Feb 12, 2015
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A method of making a semiconductor device includes forming a first opening in an insulating layer, forming a second opening in the insulating layer, forming a third opening in the insulating layer and filling the first opening, the second opening and the third opening with a conductive material. The first opening has a width and a length. The second opening has a width less than the length of the first opening, and is electrically connected to the first opening. The third opening has a width less than the width of the second opening, and is electrically connected to the second opening.

First claim

What is claimed is:

1. A method of making a semiconductor device comprising:
forming a first opening in an insulating layer, wherein the first opening has a width and a length;
forming a second opening in the insulating layer, wherein the second opening has a width less than the length of the first opening, and is electrically connected to the first opening;
forming a third opening in the insulating layer, wherein the third opening has a width less than the width of the second opening, and is electrically connected to the second opening, and forming the first opening comprises forming the first opening simultaneously with forming the third opening; and
filling the first opening, the second opening and the third opening with a conductive material.

2. The method of claim 1 , further comprising forming a via in the insulating layer, wherein the via is electrically connected to the conductive material.

3. The method of claim 1 , further comprising forming a via in another insulating layer, wherein the via is electrically connected to the conductive material.

4. The method of claim 1 , further comprising planarizing a top surface of the conductive material, wherein the top surface of the conductive material is coplanar with a top surface of the insulating layer.

5. The method of claim 1 , wherein filling the first opening comprises filling the first opening simultaneously with filling the second opening.

6. The method of claim 1 , wherein forming the first opening comprises forming the first opening simultaneously with forming the second opening.

7. The method of claim 1 , wherein forming the second opening comprises performing a photolithography process.

8. The method of claim 1 , further comprising:
forming a first via in the insulating layer, wherein the first via is electrically connected to the conductive material filling the first opening; and
forming a second via in the insulating layer, wherein the second via is electrically connected to the conductive material filling the third opening.

9. The method of claim 8 , further comprising:
forming a second insulating layer over the insulating layer; and
forming a third via in the second insulating layer, wherein the third via is electrically connected to the conductive material filling the first opening.

10. A method of making a semiconductor device comprising:
forming an opening in a first insulating layer, wherein the opening comprises a first section having a first width and a first length, a second section having a second width, and a third section having a third width, and the third width is less than the second width;
filling the opening with a conductive material;
depositing a second insulating layer over the first insulating layer and over the conductive material; and
forming a first via in the second insulating layer, wherein the first via lands on the conductive material in the third section.

11. The method of claim 10 , further comprising planarizing the conductive material prior to depositing the second insulating layer.

12. The method of claim 10 , further comprising forming a second via in the first insulating layer, wherein the second via lands on the conductive material in the first section.

13. The method of claim 12 , further comprising forming a third via in the second insulating layer, wherein the third via lands on the conductive material in the third section.

14. The method of claim 10 , wherein forming the opening comprises forming the opening comprising:
a fourth section having a fourth width, wherein the fourth width is greater than the third width, and
a fifth section having a fifth width, wherein the fifth width is greater than the fourth width.

15. The method of claim 14 , wherein forming the opening comprises forming the opening having the third section between the second section and the fourth section.

16. A method of making a semiconductor device comprising:
generating a first interconnect layout pattern, wherein the interconnect layout pattern comprises a first section having a first width and a first length, a second section having a second width a, and a third section having a third width, and the third width is less than the second width
forming an opening in a first insulating layer based on the first interconnect layout pattern, wherein forming the opening comprises simultaneously forming portions of the opening corresponding to the first section and the third section; and
filling the opening in the first insulating layer with a first conductive material.

17. The method of claim 16 , further comprising:
generating a second interconnect layout pattern; and
forming an opening in a second insulating layer based on the second interconnect layout pattern; and
filling the opening in the second insulating layer with a second conductive material.

18. The method of claim 17 , further comprising forming a via electrically connected to the first conductive material and the second conductive material.

19. The method of claim 17 , wherein forming the via comprises forming the via in the first insulating layer.

20. The method of claim 17 , wherein forming the via comprises forming the via in the second insulating layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Jian-Hong
• Chang Hsin-Chun
• CHEN Shiou-Fan
• Chiu Chwei-Ching
• Lee Yung-Huei

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/057 Primary

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title