Semiconductor device structure
US-2024013845-A1 · Jan 11, 2024 · US
Anti-fuse structure and fabrication
US9105637B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105637-B2 |
| Application number | US-201213475542-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 18, 2012 |
| Priority date | May 18, 2012 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A method including a first interconnect level including a first electrode embedded in a first dielectric layer, a top surface of the first electrode is substantially flush with a top surface of the first dielectric layer, a second interconnect level including a via embedded in a second dielectric layer above the first dielectric layer, a third dielectric layer in direct contact with and separating the first dielectric layer and the second dielectric layer, an entire top surface of the first electrode is in direct physical contact with a bottom surface of the third dielectric layer, and an interface between the first dielectric layer and the third dielectric layer extending from the top surface of the first electrode to the via, the interface including a length less than a minimum width of the via, a bottom surface of the via is in direct physical contact with the first dielectric layer.
First claim
Opening claim text (preview).
What is claimed is: 1. An anti-fuse structure comprising: a first interconnect level comprising a first electrode embedded in a first dielectric layer, a top surface of the first electrode is substantially flush with a top surface of the first dielectric layer; a second interconnect level comprising a via embedded in a second dielectric layer above the first dielectric layer; a third dielectric layer in direct contact with and separating the first dielectric layer and the seco…
Assignees
Inventors
Classifications
Electricity · mapped topic
Electricity · mapped topic
- H10W20/491Primary
Electricity · mapped topic
- H01L23/5252Primary
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9105637B2 cover?
- A method including a first interconnect level including a first electrode embedded in a first dielectric layer, a top surface of the first electrode is substantially flush with a top surface of the first dielectric layer, a second interconnect level including a via embedded in a second dielectric layer above the first dielectric layer, a third dielectric layer in direct contact with and separat…
- Who is the assignee on this patent?
- Filippi Ronald G, Lustig Naftali, Wang Ping-Chuan, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification H10W20/491. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).