Method and structure for improving vertical transistor

Patent metadata

Field	Value
Publication number	US-9935102-B1
Application number	US-201615285739-A
Country	US
Kind code	B1
Filing date	Oct 5, 2016
Priority date	Oct 5, 2016
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a first source/drain disposed in contact with a substrate. A second source/drain is disposed above the first source/drain. At least one fin structure is disposed between and in contact with the first source/drain and the second source/drain. A width of the first source/drain and the second source/drain gradually decreases towards the fin structure. The method includes forming an oxide in contact with an exposed portion of at least one fin structure. During formation of the oxide, different areas of the exposed fin structure portion are oxidized at different rates. This forms a first region and a second region of the exposed fin structure portion. These regions each have a width that is greater than a width of a third region of the exposed fin structure portion situated between the first and second regions.

First claim

What is claimed is:

1. A method for fabricating a vertical fin field-effect-transistor structure, the method comprising:
forming an oxide in contact with an exposed portion of at least one fin structure, wherein during the formation of the oxide different areas of the exposed portion of the fin structure are oxidized at different rates forming a first region and a second region of the exposed portion, wherein the first region and the second region each have a width that is greater than a width of a third region of the exposed portion situated between the first and second regions, and wherein the width of the first region and the width of the second region gradually decreases towards the third region of the exposed portion.

2. The method of claim 1 , further comprising:
forming the fin structure from a portion of a semiconductor substrate.

3. The method of claim 2 , wherein the fin structure is formed with a tapered profile.

4. The method of claim 2 , further comprising:
prior to forming the oxide, forming a first spacer on sidewalls of an upper portion of the fin structure.

5. The method of claim 4 , further comprising:
after forming the first spacer, etching a portion of the semiconductor substrate below the first spacer, the etching forming the exposed portion of the fin structure in contact with the oxide.

6. The method of claim 5 , further comprising:
etching portions of the oxide extending laterally beyond the spacers, the etching forming a second spacer from the oxide in contact with sidewalls of the first, second, and third regions of the exposed portion of the fin structure.

7. The method of claim 6 , further comprising:
forming a top source/drain within the upper portion of the fin structure; and
forming a bottom source/drain within a portion of the semiconductor substrate and the second region.

8. The method of claim 7 , wherein forming the top source/drain and the bottom source/drain further comprises:
removing the first spacer exposing the upper portion of the fin structure;
incorporating dopants into at least the upper portion of the fin structure, the second region, and a portion of the semiconductor substrate, wherein at least a portion of the third region remains undoped; and
activating the incorporated dopants.

9. The method of claim 7 , further comprising:
forming a bottom spacer in contact with the bottom source/drain and a portion of the second spacer; and
forming a cap layer in contact with a top surface of the top bottom source/drain.

10. The method of claim 9 , further comprising:
removing exposed portions of the second spacer; and
forming a gate structure in contact with the fin structure, the gate structure comprising a dielectric layer and a gate layer, wherein forming the gate structure comprises forming a concavity within a top surface of the gate layer.

11. The method of claim 10 , further comprising:
forming a top spacer in contact with gate structure and the top source/drain.

12. A method for fabricating a vertical fin field-effect-transistor structure, the method comprising:
forming at least one fin structure from a portion of a semiconductor substrate;
tapering the fin structure; and
forming an oxide in contact with an exposed portion of the at least one fin structure, wherein during the formation of the oxide different areas of the exposed portion of the fin structure are oxidized at different rates forming a first region and a second region of the exposed portion, wherein the first region and the second region each have a width that gradually decreases towards a third region of the exposed portion situated between the first and second regions.

13. The method of claim 12 , further comprising:
prior to forming the oxide, forming a first spacer on sidewalls of an upper portion of the fin structure.

14. The method of claim 13 , further comprising:
after forming the first spacer, etching a portion of the semiconductor substrate below the first spacer, the etching forming the exposed portion of the fin structure in contact with the oxide.

15. The method of claim 14 , further comprising:
etching portions of the oxide extending laterally beyond the spacers, the etching forming a second spacer from the oxide in contact with sidewalls of the first, second, and third regions of the exposed portion of the fin structure.

16. The method of claim 15 , further comprising:
forming a top source/drain within the upper portion of the fin structure; and
forming a bottom source/drain within a portion of the semiconductor substrate and the second region.

17. The method of claim 16 , wherein forming the top source/drain and the bottom source/drain further comprises:
removing the first spacer exposing the upper portion of the fin structure;
incorporating dopants into at least the upper portion of the fin structure, the second region, and a portion of the semiconductor substrate, wherein at least a portion of the third region remains undoped; and
activating the incorporated dopants.

18. The method of claim 16 , further comprising:
forming a bottom spacer in contact with the bottom source/drain and a portion of the second spacer; and
forming a cap layer in contact with a top surface of the top bottom source/drain.

19. The method of claim 18 , further comprising:
removing exposed portions of the second spacer; and
forming a gate structure in contact with the fin structure, the gate structure comprising a dielectric layer and a gate layer, wherein forming the gate structure comprises forming a concavity within a top surface of the gate layer.

Assignees

• IBM

Inventors

• Bi Zhenxing
• Cheng Kangguo
• Li Juntao
• Xu Peng

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10P14/6306

  of the semiconductor materials · CPC title

• H01L29/0692

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic