IGBT semiconductor device

Patent metadata

Field	Value
Publication number	US-9929260-B2
Application number	US-201615284550-A
Country	US
Kind code	B2
Filing date	Oct 4, 2016
Priority date	May 15, 2015
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

A semiconductor device includes a semiconductor substrate, a base region formed in the semiconductor substrate on a front surface side thereof, a gate trench extending from a front surface side of the base region and penetrating thorough the base region, and a dummy trench extending from the front surface side of the base region and penetrating thorough the base region, where a portion of the dummy trench that extends beyond a back surface of the base region is longer than a portion of the gate trench that extends beyond the back surface of the base region.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate;
a base region formed in the semiconductor substrate on a front surface side thereof;
a gate trench extending from a front surface side of the base region and penetrating thorough the base region;
a dummy trench extending from the front surface side of the base region and penetrating thorough the base region, a portion of the dummy trench that extends beyond a back surface of the base region being longer than a portion of the gate trench that extends beyond the back surface of the base region;
an accumulation region formed on a back surface of the base region, the accumulation region having a different conductivity type than the base region;
an emitter electrode provided on a front surface side of the base region; and
a floating region formed to face a back surface of the accumulation region, the floating region having a same conductivity type as the base region and being not electrically connected to the emitter electrode, wherein
the floating region is positioned closer, in a depth direction, to the base region than a bottom of the dummy trench is.

2. The semiconductor device as set forth in claim 1 , wherein
a portion of the base region through which the gate trench is formed has the same thickness as a portion of the base region through which the dummy trench is formed.

3. The semiconductor device as set forth in claim 1 , further comprising
an emitter electrode provided in the base region on a front surface side thereof, wherein
the dummy trench is connected to the emitter electrode.

4. The semiconductor device as set forth in Claim 1 wherein
the accumulation region is positioned closer to the base region than the bottom of the dummy trench is.

5. The semiconductor device as set forth in claim 4 , wherein
the accumulation region is positioned closer to a back surface of the semiconductor device than a bottom of the gate trench is and spaced away from the gate trench.

6. The semiconductor device as set forth in claim 5 , further comprising
a low-concentration region formed between the accumulation region and the bottom of the gate trench, the low-concentration region having the same conductivity type as the accumulation region and a lower impurity concentration than the accumulation region.

7. The semiconductor device as set forth in claim 1 , wherein
on the front surface side of the semiconductor substrate, an opening width of the gate trench is smaller than an opening width of the dummy trench.

8. The semiconductor device as set forth in claim 1 , wherein
the gate trench includes:
a groove formed in the semiconductor substrate on the front surface side thereof;
an insulating film formed on an inner wall of the groove; and
an electrically conductive portion formed inside the insulating film within the groove, wherein
the insulating film formed at a bottom of the groove is thicker than the insulating film formed at an opening of the groove at the front surface of the semiconductor substrate.

9. The semiconductor device as set forth in claim 4 wherein
the gate trench includes:
a groove formed in the semiconductor substrate on the front surface side thereof;
an insulating film formed on an inner wall of the groove; and
an electrically conductive portion formed inside the insulating film within the groove, wherein
the insulating film positioned closer to a bottom of the groove than the accumulation region is is at least partially thicker than the insulating film positioned closer to an opening of the groove than the accumulation region is.

10. The semiconductor device as set forth in claim 3 , wherein
the dummy trench includes:
a front-side portion extending from the front surface of the semiconductor substrate; and
a bottom-side portion provided closer to a bottom of a groove than the front-side portion, the bottom-side portion having a larger width than the front-side portion.

11. The semiconductor device as set forth in claim 3 , wherein
the gate trench and the dummy trench each include:
a groove formed in the semiconductor substrate on the front surface side thereof;
an insulating film formed on an inner wall of the groove; and
an electrically conductive portion formed inside the insulating film within the groove, wherein
the insulating film formed at a bottom of the dummy trench is thicker than the insulating film in the gate trench.

12. The semiconductor device as set forth in claim 1 , wherein
the semiconductor substrate includes:
a transistor portion having the base region, the gate trench and the dummy trench formed therein; and
a diode portion having the base region and an emitter trench formed therein, wherein
the emitter trench extends from the front surface side of the base region and penetrates through the base region.

13. The semiconductor device as set forth in claim 12 , wherein
the diode portion has a plurality of the emitter trenches that extend different lengths beyond the back surface of the base region.

14. The semiconductor device as set forth in claim 13 , wherein
at least one of the emitter trenches extends the same length beyond the back surface of the base region as the gate trench extends beyond the back surface of the base region, and
another at least one of the emitter trenches extends the same length beyond the back surface of the base region as the dummy trench extends beyond the back surface of the base region.

15. The semiconductor device as set forth in claim 12 , wherein
the diode portion has a plurality of the emitter trenches that extend the same length beyond the back surface of the base region.

16. The semiconductor device as set forth in claim 12 , wherein
a distance between adjacent ones of a plurality of the emitter trenches is the same as a distance between the gate trench and the dummy trench in the transistor portion.

17. The semiconductor device as set forth in claim 1 , further comprising
a well region formed in the semiconductor substrate on the front surface side thereof, the well region being positioned closer to an edge of the semiconductor substrate than the base region is, wherein
the dummy trench has a branch portion extending in a direction parallel to an edge of the well region at the front surface of the semiconductor substrate.

18. The semiconductor device as set forth in claim 17 , wherein
emitter regions of a first conductivity type and contact regions of a second conductivity type are alternately formed in the semiconductor substrate on the front surface side thereof, and
the branch portion is formed in one of the contact regions that is the closest to the well region.

19. The semiconductor device as set forth in claim 18 , comprising
a plurality of the dummy trenches separated from each other, wherein
the branch portions of the dummy trenches are aligned with each other on the same straight line.

20. The semiconductor device as set forth in claim 17 , further comprising
a back-surface trench formed in the semiconductor substrate on a back surface side thereof.

21. The semiconductor device as set forth in claim 20 , wherein
the back-surface trench is positioned closer to a center of the semiconductor substrate than the branch portion of the dummy trench is.

22. The semiconductor device as set forth in claim 20 , wherein
the back-surface trench is annularly formed at the back surface of the semiconductor substrate.

Assignees

• Fuji Electric Co Ltd

Inventors

• Naito Tatsuya

Classifications

• H01L29/407

  Electricity · mapped topic

• H01L29/4236

  Electricity · mapped topic

• H01L29/0804

  Electricity · mapped topic

• H01L29/0619

  Electricity · mapped topic

• H01L29/42376

  Electricity · mapped topic