Middle of the line (MOL) contacts with two-dimensional self-alignment

Patent metadata

Field	Value
Publication number	US-9929048-B1
Application number	US-201615388400-A
Country	US
Kind code	B1
Filing date	Dec 22, 2016
Priority date	Dec 22, 2016
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

Disclosed are methods of forming an integrated circuit (IC) structure with self-aligned middle of the line (MOL) contacts and the resulting IC structure. In the methods, different, selectively etchable, dielectric materials are used above the gate level for: a dielectric cap above a gate; a dielectric spacer above a gate sidewall spacer and laterally surrounding the dielectric cap; and a stack of dielectric layer(s) that covers the dielectric cap, the dielectric spacer, and metal plugs positioned laterally adjacent to the dielectric spacer and above source/drain regions. Due to the different dielectric materials, subsequently formed gate and source/drain contacts are self-aligned in two dimensions to provide protection against the occurrence of opens between wires and/or vias in the first BEOL metal level and the contacts and to further provide protection against the occurrence of shorts between the gate contact and any metal plugs and between the source/drain contacts and the gate.

First claim

What is claimed is:

1. A method comprising:
forming at least one dielectric layer over a dielectric cap, a dielectric spacer, and metal plugs,
wherein the dielectric cap is above and immediately adjacent to a gate,
wherein a gate sidewall spacer is positioned laterally immediately adjacent to the gate,
wherein the gate is above a channel region,
wherein the channel region is positioned laterally between source/drain regions,
wherein the dielectric spacer is above and immediately adjacent to a top surface of the gate sidewall spacer and laterally surrounds and is immediately adjacent to the dielectric cap, and
wherein the metal plugs are above the source/drain regions and positioned laterally adjacent to the gate sidewall spacer and the dielectric spacer that is above the gate sidewall spacer;

forming trenches in an upper portion of the at least one dielectric layer;
forming contact openings that extend from the trenches through a lower portion of the at least one dielectric layer, the contact openings comprising at least a first contact opening that extends through the lower portion and the dielectric cap to the gate and a second contact opening that extends through the lower portion to a metal plug; and
depositing metal to form wires in the trenches, a first contact in the first contact opening and a second contact in the second contact opening,
wherein the dielectric cap, the dielectric spacer, and the at least one dielectric layer comprise different dielectric materials.

2. The method of claim 1 , the different dielectric materials ensuring that the first contact and the second contact are self-aligned.

3. The method of claim 1 , the first contact opening landing on the gate adjacent to an active region.

4. The method of claim 1 ,
the at least one dielectric layer comprising: an interlayer dielectric layer; and a hardmask layer above the interlayer dielectric layer, and
the different dielectric materials being preselected so that the interlayer dielectric layer is selectively etchable against the hardmask layer, the dielectric cap and the dielectric spacer and
the different dielectric materials further being preselected so that the dielectric cap is selectively etchable against the interlayer dielectric layer, the hardmask layer and the dielectric spacer.

5. The method of claim 4 , the different dielectric materials comprising titanium nitride for the hardmask layer, silicon oxide for the interlayer dielectric layer, silicon nitride for the dielectric cap and silicon oxycarbide for the dielectric spacer.

6. The method of claim 1 , the gate sidewall spacer and the dielectric cap comprising a same dielectric material.

7. The method of claim 1 , the gate sidewall spacer and the dielectric cap comprising two different dielectric materials.

8. The method of claim 1 , the gate and the metal plugs having top surfaces at different levels.

9. A method comprising:
planarizing a first interlayer dielectric layer to expose sacrificial gates and gate sidewall spacers, each sacrificial gate being above channel regions in adjacent semiconductor bodies;
replacing the sacrificial gates with replacement metal gates;
recessing the replacement metal gates and the gate sidewall spacers;
forming dielectric spacers on exposed vertical surfaces of the first interlayer dielectric layer above the gate sidewall spacers;
forming dielectric caps on the replacement metal gates, each dielectric cap being laterally surrounded by and immediately adjacent to a dielectric spacer;
forming metal plug openings that extend through the first interlayer dielectric layer to raised source/drain regions, the raised source/drain regions being positioned laterally adjacent to the gate sidewall spacers and above source/drain regions that are in the semiconductor bodies on opposing sides of the channel regions;
forming metal plugs in the metal plug openings;
recessing the metal plugs;
forming a stack of dielectric layers over the dielectric caps, the dielectric spacers, and the metal plugs, the stack comprising a second interlayer dielectric layer and a hardmask layer on the second interlayer dielectric layer;
forming trenches in an upper portion of the stack;
forming contact openings that extend from the trenches through a lower portion of the stack, the contact openings comprising at least a first contact opening that extends through the lower portion and a dielectric cap to a replacement metal gate and a second contact opening that extends through the lower portion to a metal plug; and
depositing metal to form wires in the trenches, a first contact in the first contact opening and a second contact in the second contact opening,
wherein the dielectric caps, the dielectric spacers, and each of the dielectric layers in the stack comprise different dielectric materials.

10. The method of claim 9 , the different dielectric materials ensuring that the first contact and the second contact are self-aligned in two dimensions.

11. The method of claim 9 , the first contact opening landing on the replacement metal gate adjacent to an active region.

12. The method of claim 9 ,
the different dielectric materials being preselected so that the second interlayer dielectric layer is selectively etchable against the hardmask layer, the dielectric caps and the dielectric spacers, and
the different dielectric materials further being preselected so that the dielectric caps are selectively etchable against the second interlayer dielectric layer, the hardmask layer and the dielectric spacers.

13. The method of claim 9 , the different dielectric materials comprising titanium nitride for the hardmask layer, silicon oxide for the second interlayer dielectric layer, silicon nitride for the dielectric caps and silicon oxycarbide for the dielectric spacers.

14. The method of claim 9 , the gate sidewall spacers and the dielectric caps comprising a same dielectric material.

15. The method of claim 9 , the gate sidewall spacers and the dielectric caps comprising two different dielectric materials.

16. The method of claim 9 , the recessing being performed such that the replacement metal gates and the metal plugs having top surfaces at different levels.

17. A method comprising:
forming at least one dielectric layer over a dielectric cap, a dielectric spacer, and metal plugs,
wherein the dielectric cap is above a gate,
wherein the gate has gate sidewall spacers and is adjacent to a channel region,
wherein the channel region is positioned laterally between source/drain regions,
wherein the dielectric spacer is above the gate sidewall spacer and laterally surrounds and is immediately adjacent to the dielectric cap, and
wherein the metal plugs are above the source/drain regions and positioned laterally adjacent to the dielectric spacer;

forming trenches in an upper portion of the at least one dielectric layer;
forming contact openings that extend from the trenches through a lower portion of the at least one dielectric layer, the contact openings comprising at least a first contact opening that extends through the lower portion and the dielectric cap to the gate and a second contact opening that extends through the lower portion to a metal plug; and
depositing metal to form wires in the trenches, a first contact in the first contact opening and a second contact in the second contact opening,
wherein the at least one dielectric layer comprises: an interlayer dielectric layer; and a hardmask layer above the interlayer dielectric layer, and
wherein the hardmask layer, the interlayer dielectric layer, the di

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong
• Park Chanro
• Labonte Andre
• Liebmann Lars

Classifications

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/085

  involving intermediate temporary filling with material · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/48

  Insulating materials thereof · CPC title