Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM)

Patent metadata

Field	Value
Publication number	US-9928899-B2
Application number	US-201615388991-A
Country	US
Kind code	B2
Filing date	Dec 22, 2016
Priority date	Dec 29, 2015
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
an array of memory cells arranged in rows and columns, wherein the array includes a first subarray of memory cells and a second subarray of memory cells;
a first pair of complementary bit lines (CBLs) extending along a column of the array, from a first side of the array, and terminating between the first and second subarrays, wherein the first pair of CBLs is electrically coupled to memory cells of the first subarray in the column;
a second pair of CBLs extending from the first side of the array, along the column, to a second side of the array, wherein the second pair of CBLs is electrically coupled to memory cells of the second subarray in the column, and wherein the CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays; and
a third pair of CBLs and a fourth pair of CBLs extending along the column, wherein the third and fourth pairs of CBLs are electrically coupled respectively to the memory cells of the first subarray in the column and the memory cells of the second subarray in the column.

2. The semiconductor memory device according to claim 1 , wherein the third pair of CBLs extends along the column, from the first side of the array, and terminates between the first and second subarrays, and wherein the fourth pair of CBLs extends from the first side of the array, along the column, to the second side of the array, and wherein the CBLs of the fourth pair of CBLs have stepped profiles between the first and second subarrays.

3. The semiconductor memory device according to claim 1 , wherein the third pair of CBLs extends from the second side of the array, along the column, to the first side of the array, and wherein the CBLs of the third pair of CBLs have stepped profiles between the first and second subarrays, and wherein the fourth pair of CBLs extends along the column, from the second side of the array, and terminates between the first and second subarrays.

4. The semiconductor memory device according to claim 3 , further comprising:
a first multiplexer on the first side of the array and configured to select between the first pair of CBLs and the second pair of CBLs; and
a second multiplexer on the second side of the array and configured to select between the third pair of CBLs and the fourth pair of CBLs.

5. The semiconductor memory device according to claim 1 , wherein a CBL of the second pair of CBLs comprises:
a fly bit line segment extending laterally along the column, from the first side of the array, and terminating between the first and second subarrays;
a local bit line segment extending from between the first and second subarrays, laterally along the column, to the second side of the array, wherein the local bit line segment is spaced below the fly bit line segment in a direction orthogonal to the rows and the columns; and
a jump cell between the first and second subarrays, wherein the jump cell electrically couples the fly bit line segment to the local bit line segment.

6. The semiconductor memory device according to claim 5 , wherein the fly bit line segment and the local bit line segment are laterally spaced in a direction parallel to the rows.

7. The semiconductor memory device according to claim 1 , further comprising:
a twist cell configured to twist neighboring bit lines respectively from two pairs of CBLs extending along the column, wherein the two pairs of CBLs correspond to two of the first, second, third, and fourth pairs of CBLs.

8. The semiconductor memory device according to claim 7 , wherein the neighboring bit lines comprise a first bit line extending to the twist cell along a first axis, and further comprise a second bit line extending to the twist cell along a second axis that is parallel to the first axis and the column, wherein the first bit line extends from the twist cell along the second axis, and wherein the second bit line extends from the twist cell along the first axis.

9. The semiconductor memory device according to claim 8 , wherein the twist cell is spaced between the memory cells of the first subarray in the column, wherein the two pairs of CBLs correspond to the first and third pairs of CBLs, and wherein the second or fourth pair of CBLs comprises a bit line extending along a third axis that is parallel to the first and second axes and that is between the first and second axes, and wherein the bit line extends over the twist cell while extending along the third axis.

10. The semiconductor memory device according to claim 8 , wherein the twist cell is spaced between the memory cells of the second subarray in the column, wherein the two pairs of CBLs correspond to the second and fourth pairs of CBLs, and wherein the third pair of CBLs comprises a bit line extending along a third axis that is parallel to the first and second axes and that is between the first and second axes, and wherein the bit line extends over the twist cell while extending along the third axis.

11. The semiconductor memory device according to claim 1 , wherein a first memory cell in the first subarray and a second memory cell in the second subarray are dual-port static random-access memory (DP SRAM) cells, wherein dual ports of the first memory cell are electrically coupled respectively to the first pair of CBLs and the third pair of CBLs, and wherein dual ports of the second memory cell are electrically coupled respectively to the second pair of CBLs and the fourth pair of CBLs.

12. A semiconductor memory device comprising:
an array of memory cells arranged in rows and columns, wherein the array includes a first subarray of memory cells and a second subarray of memory cells;
a first pair of complementary bit lines (CBLs) extending along a column of the array, from a first side of the array, and terminating between the first and second subarrays, wherein the first pair of CBLs is electrically coupled to memory cells of the first subarray in the column;
a second pair of CBLs extending from the first side of the array, along the column, to a second side of the array, wherein the second pair of CBLs is electrically coupled to memory cells of the second subarray in the column;
a third pair of CBLs and a fourth pair of CBLs extending along the column, wherein the third and fourth pairs of CBLs are electrically coupled respectively to the memory cells of the first subarray in the column and the memory cells of the second subarray in the column; and
a twist cell configured to twist a pair of neighboring bit lines respectively from two pairs of CBLs extending along the column, wherein the two pairs of CBLs correspond to two of the first, second, third, and fourth pairs of CBLs.

13. The semiconductor memory device according to claim 12 , further comprising:
a second twist cell configured to twist another pair of neighboring bit lines respectively from the two pairs of CBLs, wherein the neighboring bit lines of the other pair of neighboring bit lines are respectively complementary with the neighboring bit lines of the pair of neighboring bit lines.

14. The semiconductor memory device according to claim 12 , wherein the neighboring bit lines comprise a first bit line extending to the twist cell along a first axis, and further comprise a second bit line extending to the twist cell along a second axis that is parallel to the first axis and the column, wherein the first bit line extends from the twist cell along the second axis, and wherein the second bit line extends from the twist cell along the first axis.

15. The semiconductor memory device according to claim 12 , wherein the neighboring bit lines comprise

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Singh Sahil Preet
• Chen Jung-Hsuan
• Chen Yen-Huei
• Chander Avinash
• Ying Albert

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• G11C7/1075

  for multiport memories each having random access ports and serial ports, e.g. video RAM · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C8/16

  Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups · CPC title