Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM)
US-10991423-B2 · Apr 27, 2021 · US
Chander Avinash is listed as an inventor on 12 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Chander Avinash |
| Total patents | 12 |
| First publication | Jun 29, 2017 |
| Latest publication | Apr 27, 2021 |
Publications ranked by popularity score, then publication date.
US-10991423-B2 · Apr 27, 2021 · US
US-10790015-B2 · Sep 29, 2020 · US
US-2020020392-A1 · Jan 16, 2020 · US
US-2020020391-A1 · Jan 16, 2020 · US
US-10490267-B2 · Nov 26, 2019 · US
US-2019108875-A1 · Apr 11, 2019 · US
US-10157666-B2 · Dec 18, 2018 · US
US-2018137910-A1 · May 17, 2018 · US
US-9928899-B2 · Mar 27, 2018 · US
US-9812191-B1 · Nov 7, 2017 · US
Latest publications not already listed above.
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Taiwan Semiconductor Mfg Co Ltd | 12 |
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C7/12 | 12 |
| G11C11/419 | 11 |
| G11C11/418 | 11 |
| G11C7/18 | 11 |
| H10W20/43 | 11 |