Layout of static random access memory array

Patent metadata

Field	Value
Publication number	US-9558809-B1
Application number	US-201514974913-A
Country	US
Kind code	B1
Filing date	Dec 18, 2015
Priority date	Dec 18, 2015
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A column of a static random access memory (SRAM) array includes a first subarray including a first plurality of SRAM cells and a second subarray including a second plurality of SRAM cells. Each of the first and second plurality of SRAM cells includes first through fourth source active regions by which source regions of transistors thereof are formed. The column of the SRAM array includes a first bitline formed by the third source active regions of the first plurality of SRAM cells, a second bitline formed by the third source active regions of the second plurality of SRAM cells and spaced apart from the first bitline, and a third bitline formed by a metal layer extending over the third source active regions of the first and second plurality of SRAM cells and electrically connected to the second bitline but not to the first bitline.

First claim

What is claimed is:

1. A static random access memory (SRAM) array, comprising:
a first subarray including a first plurality of SRAM cells and a second subarray including a second plurality of SRAM cells,
wherein the first and second plurality of SRAM cells are arranged in one column of the SRAM array,
each of the first and second plurality of SRAM cells includes first through fourth source active regions by which source regions of transistors thereof are formed, and
the one column of the SRAM array comprises:
a first bitline formed by the third source active regions of the first plurality of SRAM cells;
a second bitline formed by the third source active regions of the second plurality of SRAM cells and spaced apart from the first bitline; and
a third bitline formed by a metal layer extending over the third source active regions of the first and second plurality of SRAM cells and electrically connected to the second bitline but not to the first bitline.

2. The SRAM array of claim 1 , wherein no electrical connection between the second bitline and the third bitline is formed within any of the second plurality of SRAM cells.

3. The SRAM array of claim 1 , wherein:
the SRAM array further includes first and second regions, the first subarray disposed between the first region and the second region and the second region disposed between the first and second subarrays,
the third bitline extends from the first region to the second subarray,
the second bitline is electrically connected to the third bitline at the second region, and
each of the source active regions is covered by an electrically conductive layer having an electrical conductivity greater than that of each of the source active region.

4. The SRAM array of claim 3 , wherein the each column of the SRAM array further comprises:
a first complementary bitline formed by the fourth source active regions of the first plurality of SRAM cells;
a second complementary bitline formed by the fourth source active regions of the second plurality of SRAM cells and spaced apart from the first complementary bitline at the second region; and
a third complementary bitline formed by a metal layer extending over the fourth source active regions of the first and second plurality of SRAM cells and electrically connected to the second complementary bitline at the second region but not to the first complementary bitline.

5. The SRAM array of claim 4 , further comprising:
a fourth bitline formed by a metal layer and electrically connected to the first bitline at the first region;
a fourth complementary bitline formed by a metal layer and electrically connected to the first complementary bitline at the first region; and
a multiplexor including first through fourth input terminals electrically connected to the fourth bitline, the fourth complementary bitline, the third bitline, and the third complementary bitline, respectively, and outputting data transmitted by the first bitline and the first complementary bitline or transmitted by the second bitline and the second complementary bitline in accordance to a selection signal applied thereto.

6. The SRAM array of claim 3 , further comprising a third region,
wherein the second subarray is interposed between the second and third regions, and
the second bitline is electrically connected to the third bitline at the third region.

7. The SRAM array of claim 3 , further comprising a fourth region between two adjacent SRAM cells of the second plurality of SRAM cells,
wherein the second bitline is electrically connected to the third bitline at the fourth region.

8. The SRAM array of claim 3 , further comprising:
a first power supply line formed by the first source active regions of the first and second plurality of SRAM cells;
a second power supply line formed by the second source active regions of the first and second plurality of SRAM cells;
a third power supply line formed by a metal layer located above the first source active regions of the first and second plurality of SRAM cells and electrically connected to the first power supply line; and
a fourth power supply line formed by a metal layer located above the second source active regions of the first and second plurality of SRAM cells and electrically connected to the second power supply line,
wherein the first and second power supply lines are respectively electrically connected to the third and fourth power supply lines at least at one of the first and second regions.

9. The SRAM array of claim 8 , wherein:
the SRAM array further comprises a plurality of wordlines,
the plurality of wordlines are formed by a metal layer between the third bitline and the third source active regions of the first and second plurality of SRAM cells, and
the metal layer forming the third and fourth power supply lines is located between the first and second source active regions of the first and second plurality of SRAM cells and the metal layer forming the plurality of wordlines.

10. The SRAM array of claim 8 , wherein:
the SRAM array further comprises a plurality of wordlines,
the plurality of wordlines are formed by a metal layer between the third bitline and the third source active regions of the first and second plurality of SRAM cells, and
the metal layer forming the third and fourth power supply lines is located at the same metal layer as the third bitline.

11. The SRAM array of claim 1 , further comprising a plurality of wordlines formed by a metal layer,
wherein the third bitline is interposed between the plurality of wordlines and the third source active regions of the first and second plurality of SRAM cells.

12. The SRAM array of claim 1 , further comprising a plurality of wordlines formed by a metal layer,
wherein the plurality of wordlines are interposed between the third bitline and the third source active regions of the first and second plurality of SRAM cells.

13. The SRAM array of claim 1 , wherein each SRAM cell comprises:
first and second P-type pull-up transistors formed in the first source active region;
first and second N-type pull-down transistors formed in the second source active region; and
first and second pass-gate transistors formed in the third and fourth source active regions, respectively, and
the fourth, first, second and third source active regions are sequentially arranged in a direction perpendicular to the one column.

14. The SRAM array of claim 13 , wherein each SRAM cell further comprises:
a first top plate electrically connected to drain regions of the first pass-gate transistor, the first N-type pull-down transistor, and the P-type first pull-up transistor;
a second top plate electrically connected to drain regions of the second pass-gate transistor, the second N-type pull-down transistor, and the second P-type pull-up transistor;
a first local connection contact electrically connecting the first top plate and gate electrodes of the second P-type pull-up transistor and the second N-type pull-down transistor to each other; and
a second local connection contact electrically connecting the second top plate and gate electrodes of the first P-type pull-up transistor and the first N-type pull-down transistor to each other.

15. The SRAM array of claim 13 , wherein each transistor is a vertical field effect transistor.

16. A static random access memory (SRAM) array, comprising:
a first subarray including a first plurality of SRAM cells and a second subarray including a second plurality of SRAM cells,
wherein the first and second plurality of SRAM cells are arranged in one column of the SRAM array,

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liaw Jhon Jhy

Classifications

• G11C11/4125

  Cells incorporating circuit means for protecting against loss of information · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• G11C11/417 Primary

  for memory cells of the field-effect type · CPC title

• H01L27/11

  Electricity · mapped topic

• H10D89/10

  Integrated device layouts · CPC title