Non-linear transmit biasing for a serial bus transmitter

Patent metadata

Field	Value
Publication number	US-9928194-B2
Application number	US-201514954133-A
Country	US
Kind code	B2
Filing date	Nov 30, 2015
Priority date	Nov 30, 2015
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

Described embodiments provide a transmitter for transmitting data over a serial bus coupled to the transmitter. The transmitter includes a controller to generate data for transmission by the transmitter. A transmit driver is coupled to the controller. The transmit driver, in response to the generated data for transmission, generates logic transitions on the serial bus. The transmit driver generates low-to-high logic transitions on the serial bus by charging the serial bus by a bus current based on (i) a predetermined initial bias level for a first time period, and (ii) a first predetermined maximum bias level for a second time period. The transmit driver generates high-to-low logic transitions on the serial bus by discharging the serial bus by a bus current based on (i) a pre-charged level of the transmit driver, and (ii) a second predetermined maximum bias level for a third time period.

First claim

We claim:

1. A transmitter comprising:
a controller configured to generate data for transmission by the transmitter over a serial bus coupled to the transmitter; and
a transmit driver coupled to the controller, the transmit driver configured to, in response to the generated data for transmission:
generate low-to-high logic transitions on the serial bus by charging the serial bus by a bus current based on (i) a predetermined initial bias level for a first time period, and (ii) a first predetermined maximum bias level for a second time period; and
generate high-to-low logic transitions on the serial bus by discharging the serial bus by a bus current based on (i) a pre-charged level of the transmit driver, and (ii) a second predetermined maximum bias level for a third time period;

wherein the transmit driver comprises:
an output transistor having an output node coupled to the serial bus, the output transistor configured to:
generate low-to-high logic transitions on the serial bus wherein the controller is configured to (i) set a bias level of the output transistor to the predetermined initial bias level by a first bias current, and (ii) linearly change the bias level from the predetermined initial bias level to a second bias level by a predetermined second bias current, whereby the output transistor is configured to non-linearly charge the output node;
generate high-to-low logic transitions on the serial bus wherein the controller is configured to (i) pre-charge the bias level of the output transistor to a pre-charge bias level by a pre-charge bias current, and (ii) linearly change the bias level from the pre-charge bias level to a fourth bias level, whereby the output transistor is configured to non-linearly discharge the output node.

2. The transmitter of claim 1 , wherein the output transistor comprises a metal-oxide semiconductor field effect transistor (MOSFET).

3. The transmitter of claim 2 , wherein:
the output transistor comprises an N-channel MOSFET;
wherein the N-channel MOSFET is configured to generate low-to-high logic transitions on the serial bus when the controller is configured to (i) set the bias level of a gate of the output transistor to the predetermined initial bias level, and (ii) linearly discharge the gate from the predetermined initial bias level to the second bias level, wherein the second bias level is a minimum bias threshold of the MOSFET;
wherein the N-channel MOSFET is configured to generate high-to-low logic transitions on the serial bus when the controller is configured to (i) pre-charge the gate of the output transistor to the pre-charge bias level by a pre-charge bias current, and (ii) linearly charge the gate from the pre-charge bias level to the fourth bias level, wherein the fourth bias level is a maximum bias threshold of the MOSFET; and
wherein the output node is non-linearly charged and discharged by changing a drain-to-source current through the MOSFET according to a squared value of the bias level.

4. The transmitter of claim 2 , wherein:
the output transistor comprises a P-channel MOSFET;
wherein the P-channel MOSFET is configured to generate low-to-high logic transitions on the serial bus when the controller is configured to (i) pre-charge a gate of the output transistor to a pre-charge bias level by a pre-charge bias current, and (ii) linearly charge the gate from the pre-charge bias level to a maximum bias threshold of the MOSFET;
wherein the P-channel MOSFET is configured to generate high-to-low logic transitions on the serial bus when the controller is configured to (i) set the gate of the output transistor to a predetermined initial bias level, and (ii) linearly discharge the gate from the predetermined initial bias level to a minimum bias threshold of the MOSFET; and
wherein the output node is non-linearly charged and discharged by changing a drain-to-source current through the MOSFET according to a squared value of the bias level.

5. The transmitter of claim 1 , wherein the output transistor comprises a bipolar junction transistor (BJT).

6. The transmitter of claim 5 , wherein:
the output transistor comprises an NPN doped BJT;
wherein the NPN BJT is configured to generate low-to-high logic transitions on the serial bus when the controller is configured to (i) set a bias level of a base of the output transistor to a predetermined initial bias level, and (ii) linearly discharge the base from the predetermined initial bias level to the second bias level, wherein the second bias level is a minimum bias threshold of the BJT;
the NPN BJT configured to generate high-to-low logic transitions on the serial bus when the controller is configured to (i) pre-charge the base to the pre-charge bias level, and (ii) linearly charge the base from the pre-charge bias level to the fourth bias level, wherein the fourth bias level is a maximum bias threshold of the BJT; and
wherein the output node is non-linearly charged and discharged by changing a collector-to-emitter current through the NPN BJT proportionally to an exponential of the bias level.

7. The transmitter of claim 5 , wherein:
the output transistor comprises a PNP doped BJT;
wherein the PNP BJT is configured to generate low-to-high logic transitions on the serial bus when the controller is configured to (i) pre-charge a base of the output transistor to a pre-charge bias level by a pre-charge bias current, and (ii) linearly charge the base from the pre-charge bias level to a maximum bias threshold of the BJT;
wherein the PNP BJT is configured to generate high-to-low logic transitions on the serial bus when the controller is configured to (i) set the base of the output transistor to a predetermined initial bias level, and (ii) linearly discharge the base from the predetermined initial bias level to a minimum bias threshold of the BJT; and
wherein the output node is non-linearly charged and discharged by changing a collector-to-emitter current through the PNP BJT proportionally to an exponential of the bias level.

8. The transmitter of claim 1 , wherein the controller is configured to linearly change the bias level from the predetermined initial bias level to the second bias level in a first predetermined time duration.

9. The transmitter of claim 1 , wherein the controller is configured to linearly change the bias level from the pre-charge bias level to the fourth bias level in a second predetermined time duration.

10. The transmitter of claim 1 , wherein the controller is configured to calibrate the transmitter.

11. The transmitter of claim 10 , wherein, for the calibration, the controller is configured to:
estimate one or more parasitic components of the serial bus; and
set at least one of the predetermined initial bias level, the second bias level, the pre-charge bias level, the maximum bias level, the minimum bias level, the first predetermined time duration, and the second predetermined time duration based, at least in part, on the estimated one or more parasitic components of the serial bus.

12. The transmitter of claim 1 , wherein the transmit driver further comprises:
an amplifier configured to (i) buffer a control signal from the processor to the output transistor and (ii) generate an amplified bias signal, based on the control signal, to the output transistor.

13. The transmitter of claim 12 , wherein the transmit driver further comprises:
at least one current mirror circuit configured to drive the output transistor based on at least one of the control signal and the amplified bias signal.

14. The transmitter of claim 1 , wherein the transmitter is configured to operate open loop.

15. T

Assignees

• Allegro Microsystems Llc

Inventors

• Ross Thomas
• Togneri Aldo
• Mcintosh James
• Allegrini Gianluca

Classifications

• H03K5/08

  by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding (H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30) · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• H04L2012/40234

  Local Interconnect Network LIN · CPC title

• G06F13/404

  with address mapping · CPC title

• H04L12/40032

  Details regarding a bus interface enhancer · CPC title