Output driver having improved electromagnetic compatibility (EMC) and associated methods

Patent metadata

Field	Value
Publication number	US-8957715-B2
Application number	US-201213653824-A
Country	US
Kind code	B2
Filing date	Oct 17, 2012
Priority date	Oct 17, 2012
Publication date	Feb 17, 2015
Grant date	Feb 17, 2015

Abstract

An integrated circuit includes an output driver circuit having a plurality of output driver devices connected in a parallel arrangement and an output driver controller that is capable of individually controlling the conducting states of the output driver devices. In at least one embodiment, the controller is capable of achieving any of a plurality of different fall times (and/or rise times) in an output signal by appropriately controlling the conducting states of the output devices if a change in the state of the output signal is desired, in some implementations, the controller is capable of achieving different waveshapes during rising and/or failing edges of an output signal.

First claim

What is claimed is:

1. An integrated circuit comprising:
an output driver circuit to generate an output signal for the integrated circuit, the output driver circuit comprising multiple driver devices connected in parallel, each of the multiple driver devices having a gate terminal, a drain terminal, and a source terminal, wherein the drain terminals of the multiple driver devices are coupled to a first node and the source terminals of the multiple driver devices are coupled to a second node; and
a controller to provide individual control signals to gate terminals of the multiple driver devices to control a state of the output signal, the controller having a change state input to receive an indication to change the state of the output signal and one or more select inputs responsive to a code word indicating a manner in which the multiple driver devices are to change conducting state when the state of the output signal is being changed;
wherein the controller is configured to change the conducting state of the multiple driver devices in sequence according to a first clock frequency in response to a first predetermined code word being present at the one or more select inputs and the controller is configured to change the conducting state of the multiple driver devices in sequence according to a second clock frequency in response to a second predetermined code word being present at the one or more select inputs, wherein the second predetermined code word is different from the first predetermined code word and the second clock frequency is different from the first clock frequency.

2. The integrated circuit of claim 1 , wherein:
the controller is configured to change the conducting states of the multiple driver devices simultaneously in response to a predetermined code word being present at the one or more select inputs.

3. The integrated circuit of claim 1 , wherein:
the controller is configured to change the conducting states of the multiple driver devices one by one in sequence in response to a predetermined code word being present at the one or more select inputs.

4. The integrated circuit of claim 1 , wherein:
the controller is configured to change the conducting states of the multiple driver devices in sequence according to first predefined device groups in response to the first predetermined code word being present at the one or more select inputs.

5. The integrated circuit of claim 4 , wherein:
the controller is configured to change the conducting states of the multiple driver devices in sequence according to second predefined device groups in response to the second predetermined code word being present at the one or more select inputs, wherein the second predefined device groups are different from the first predefined device groups.

6. The integrated circuit of claim 1 , wherein:
the controller includes a clock input to receive a clock signal to provide a timing reference for changing the conducting states of the multiple driver devices.

7. The integrated circuit of claim 6 , wherein:
the first clock frequency is the frequency of the input clock signal divided down by a first factor and the second clock frequency is the frequency of the input clock signal divided down by a second factor that is different from the first factor.

8. The integrated circuit of claim 1 , wherein:
the controller is configured to change the conducting state of the multiple driver devices in sequence according first predefined device groups in response to either the first predetermined code word or the second predetermined code word being present at the one or more select inputs.

9. The integrated circuit of claim 1 , further comprising:
a nonvolatile memory associated with the one or more select inputs of the controller for use in storing a programmed code word.

10. The integrated circuit of claim 1 , wherein:
the multiple driver devices connected in parallel include multiple n-channel insulated gate field effect transistors (IGFETs).

11. The integrated circuit of claim 10 , wherein:
the output driver circuit further comprises multiple p-channel IGFETs connected in parallel, wherein the multiple n-channel IGFETs and the multiple p-channel IGFETs are connected in a push-pull configuration, wherein the controller is configured to provide individual control signals to each of the multiple p-channel IGFETs and each of the multiple n-channel IGFETs to control the state of the output signal.

12. The integrated circuit of claim 1 , further comprising:
sensor circuitry coupled to the controller for sensing a physical quantity in a surrounding environment.

13. The integrated circuit of claim 12 , wherein the sensor circuitry comprises a magnetic field sensor.

14. The integrated circuit of claim 13 , wherein:
the magnetic field sensor comprises at least one of a Hall effect element or a magnetoresistance element.

15. The integrated circuit of claim 13 , wherein:
the magnetic field sensor comprises both a Hall effect element and a magnetoresistance element.

16. The integrated circuit of claim 1 , further comprising:
an integrated circuit package carrying the integrated circuit.

17. An integrated circuit comprising:
an output driver circuit to generate an output signal for the integrated circuit, the output driver circuit comprising multiple driver devices connected in parallel, each of the multiple driver devices having a gate terminal, a drain terminal, and a source terminal, wherein the drain terminals of the multiple driver devices are coupled to a first node and the source terminals of the multiple driver devices are coupled to a second node; and
a controller to provide individual control signals to gate terminals of the multiple driver devices to control a state of the output signal, the controller being configured to change conducting states of the multiple driver devices in a sequential manner if a change in the state of the output signal is desired;
wherein the controller is configured to change the conducting states of the multiple driver devices in a sequential manner in accordance with a clock signal having a frequency that is set according to a code word stored in a non-volatile memory of the integrated circuit.

18. The integrated circuit of claim 17 , wherein:
the controller is configured to change the conducting states of the multiple driver devices one by one in a sequential manner if a change in the state of the output signal is desired.

19. The integrated circuit of claim 17 , wherein:
the controller is configured to change the conducting states of the multiple driver devices in a sequential manner according to predefined groups if a change in the state of the output signal is desired.

20. The integrated circuit of claim 17 , wherein:
the controller is configured to change the conducting states of the multiple driver devices in a sequential manner in accordance with a first clock frequency if the code word stored in the non-volatile memory is a first predetermined codeword and the controller is configured to change the conducting states of the multiple driver devices in a sequential manner in accordance with a second clock frequency if the code word stored in the non-volatile memory is a second predetermined codeword, wherein the second predetermined codeword is different from the first predetermined codeword and the second clock frequency is different from the first clock frequency.

21. The integrated circuit of claim 20 , wherein:
the controller includes a clock input to r

Assignees

• Eagen Jeff
• Allegro Microsystems Llc

Inventors

• Eagen Jeff

Classifications

• H03K17/164 Primary

  using parallel switching arrangements · CPC title

• H10N52/00

  Hall-effect devices (integrated devices or assemblies of multiple devices H10N59/00) · CPC title