Selective, electrochemical etching of a semiconductor

Patent metadata

Field	Value
Publication number	US-9922838-B2
Application number	US-201515116041-A
Country	US
Kind code	B2
Filing date	Feb 10, 2015
Priority date	Feb 10, 2014
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

Methods for facilitating fabricating semiconductor structures are provided which include: providing a multilayer structure including a semiconductor layer, the semiconductor layer including a dopant and having an increased conductivity; selectively increasing, using electrochemical processing, porosity of the semiconductor layer, at least in part, the selectively increasing porosity utilizing the increased conductivity of the semiconductor layer; and removing, at least in part, the semiconductor layer with the selectively increased porosity from the multilayer structure. By way of example, the selectively increasing porosity may include selectively, anodically oxidizing, at least in part, the semiconductor layer of the multilayer structure.

First claim

What is claimed is:

1. A method comprising:
providing a multilayer structure comprising a first semiconductor layer and a second semiconductor layer, the first semiconductor layer and the second semiconductor layer each comprising silicon carbide or a silicon carbide alloy, the first semiconductor layer comprising a higher concentration of a dopant and a higher conductivity than the second semiconductor layer, the first semiconductor layer being an n+layer,;
selectively increasing, by electrochemical processing the first semiconductor layer within an electrolytic solution comprising an inorganic acid and an oxidizing species, porosity of the first semiconductor layer, at least in part, the selectively increasing porosity utilizing the higher conductivity of the first semiconductor layer; and
removing, at least in part, the first semiconductor layer with the selectively increased porosity from the multilayer structure.

2. The method of claim 1 , wherein the selectively increasing porosity comprises selectively anodically oxidizing, at least in part, the first semiconductor layer.

3. The method of claim 2 , wherein the electrochemically processing selectively anodically oxidizes, at least in part, the first semiconductor layer, the higher concentration of dopant of the first semiconductor layer enhancing the anodically oxidizing thereof to selectively increase the porosity of the first semiconductor layer and facilitate the removing, at least in part, of the first semiconductor layer from the multilayer structure.

4. The method of claim 3 , wherein the electrochemically processing comprises controlling a current density applied through the electrolytic solution and the first semiconductor layer, the selectively increasing porosity being, at least in part, a function of the current density applied.

5. The method of claim 2 , wherein the providing comprises epitaxially growing the second semiconductor layer over the first semiconductor layer prior to the selectively increasing porosity of the first semiconductor layer.

6. The method of claim 5 , wherein the first semiconductor layer and the second semiconductor layer each comprise a wide-bandgap semiconductor material.

7. The method of claim 5 , wherein the anodically oxidizing of the first semiconductor layer utilizing the greater conductivity of the first semiconductor layer to selectively increase porosity of the first semiconductor layer, at least in part, without increasing porosity of the second semiconductor layer.

8. The method of claim 7 , wherein the first conductivity of the first semiconductor layer is ten times greater or more than the second conductivity of the second semiconductor layer.

9. The method of claim 1 , wherein the providing comprises providing the first semiconductor layer and the second semiconductor layer as a semiconductor substrate of the multilayer structure, the selectively increasing porosity facilitating removing, at least in part, the first semiconductor layer of the semiconductor substrate.

10. The method of claim 9 , wherein the providing the multilayer structure further comprises providing a multilayer semiconductor device above the first semiconductor layer and the second semiconductor layer prior to the selectively increasing porosity of the first semiconductor layer.

11. The method of claim 10 , wherein the multilayer semiconductor device comprises a p-i-n diode.

12. The method of claim 10 , wherein the multilayer semiconductor device comprises a Schottky diode.

13. The method of claim 1 , wherein the providing the multilayer structure comprises providing the first semiconductor layer and the second semiconductor layer above a semiconductor substrate, the selectively increasing porosity and the removing, at least in part, the first semiconductor layer, facilitating removing the semiconductor substrate from the multilayer structure.

14. The method of claim 13 , wherein the providing the multilayer structure further comprises providing a multilayer semiconductor device above the first semiconductor layer and the second semiconductor layer prior to the selectively increasing porosity of the first semiconductor layer.

15. The method of claim 14 , further comprising bonding the multilayer structure to a support substrate prior to the removing of the semiconductor substrate of the multilayer structure.

16. The method of claim 1 , wherein the removing comprises only partially removing the first semiconductor layer from the multilayer structure, leaving the thinned first semiconductor layer as part of the multilayer structure.

17. The method of claim 16 , wherein the providing the multilayer structure further comprises providing a multilayer semiconductor device above the first semiconductor layer and the second semiconductor layer.

18. The method of claim 16 , wherein the providing comprises providing the first semiconductor layer and the second semiconductor layer as a semiconductor substrate of the multilayer structure, the thinned first semiconductor layer being a thinned semiconductor substrate of the multilayer structure.

Assignees

• Rensselaer Polytech Inst

Inventors

• Dahal Rajendra P
• Bhat Ishwara B
• Chow Tat-Sing

Classifications

• H10P95/408

  of Group III-V semiconductors, e.g. to render them semi-insulating · CPC title

• H10P95/70

  Chemical treatments · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/613

  of Group IV materials · CPC title

• H10P50/20 Primary

  Dry etching; Plasma etching; Reactive-ion etching · CPC title