Reducing select gate injection disturb at the beginning of an erase operation

Patent metadata

Field	Value
Publication number	US-9922705-B1
Application number	US-201715621222-A
Country	US
Kind code	B1
Filing date	Jun 13, 2017
Priority date	Jun 13, 2017
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel gradient near the select gate transistors is reduced when the voltages of the drain and source ends of a memory string are increased to an erase level which charges up the channel. In one approach, the voltage of the word line which is adjacent to a select gate line is temporarily increased. Another approach builds off the first approach by temporarily increasing the voltage of the select gate line at the same time as the increase in the word line voltage.

First claim

We claim:

1. An apparatus, comprising:
a memory string comprising a set of memory cells between a source end of the memory string and a drain end of the memory string, a select gate transistor at the drain end, and a channel extending from the source end to the drain end, wherein the set of memory cells comprises a memory cell adjacent to the select gate transistor as an adjacent memory cell, and other memory cells; and
a control circuit, the control circuit, to perform an erase operation for the set of memory cells, is configured to:
increase a voltage at the source end, from a respective initial level to an erase level which charges up the channel;
during the increase of the voltage at the source end, increase a control gate voltage of the adjacent memory cell, from a respective initial level to a respective peak level, and increase a control gate voltage of the select gate transistor, from a respective initial level to a respective peak level; and
while the channel is charged up, decrease the control gate voltage of the adjacent memory cell, from the respective peak level to a respective lower level and hold the control gate voltage of the adjacent memory cell at the respective lower level to erase the adjacent memory cell, and hold control gate voltages of the other memory cells at a respective fixed level to erase the other memory cells.

2. The apparatus of claim 1 , wherein:
the control circuit, to perform the erase operation, is configured to hold the control gate voltage of the select gate transistor at the respective peak level during the hold of the control gate voltage of the adjacent memory cell at the respective lower level and the hold of the control gate voltages of the other memory cells at the respective fixed level.

3. The apparatus of claim 2 , wherein:
the charge up of the channel occurs, at least in part, during the hold of the control gate voltage of the adjacent memory cell at the respective peak level and during the hold of the control gate voltage of the select gate transistor at the respective peak level.

4. The apparatus of claim 1 , wherein:
the control circuit, to perform the erase operation, is configured to decrease the control gate voltage of the select gate transistor from the respective peak level to an intermediate level which is between the respective peak level and the respective initial level, and hold the control gate voltage of the select gate transistor at the intermediate level during the hold of the control gate voltage of the adjacent memory cell at the respective lower level and during the hold of the control gate voltages of the other memory cells at the respective fixed level.

5. The apparatus of claim 4 , wherein:
the control circuit, to perform the erase operation, is configured to set the respective peak level of the control gate voltage of the select gate transistor as a function of the erase level; and
the respective peak level of the control gate voltage of the select gate transistor is relatively higher when the erase level is relatively higher.

6. The apparatus of claim 4 , wherein:
the erase operation comprises a plurality of erase loops; and
the control circuit, to perform the erase operation, is configured to increase the erase level and the respective peak level of the control gate voltage of the select gate transistor over successive erase loops of the plurality of erase loops.

7. The apparatus of claim 4 , wherein:
the erase operation comprises a plurality of erase loops; and
the control circuit, to perform the erase operation, is configured to increase the erase level and a time period of the hold the control gate voltage of the select gate transistor at the respective peak level over successive erase loops of the plurality of erase loops.

8. The apparatus of claim 4 , wherein:
a time period of the hold the control gate voltage of the select gate transistor at the respective peak level is set based on a temperature; and
the time period is relatively shorter when the temperature is relatively higher.

9. The apparatus of claim 4 , wherein:
the decrease of the control gate voltage of the select gate transistor from the respective peak level to the intermediate level occurs during the decrease of the control gate voltage of the adjacent memory cell.

10. The apparatus of claim 1 , wherein:
a time period of the hold the control gate voltage of the adjacent memory cell at the respective peak level is set based on a temperature; and
the time period is relatively shorter when the temperature is relatively higher.

11. The apparatus of claim 1 , wherein:
the control circuit, to perform the erase operation, is configured to increase a voltage at the drain end, from a respective initial level to an erase level which charges up the channel.

12. The apparatus of claim 1 , wherein:
the adjacent memory cell is a dummy memory cell and the other memory cells comprise data memory cells.

13. A method for erasing memory cells, comprising:
charging up a channel of a memory string, wherein the memory strings comprises a set of memory cells between a source end of the memory string and a drain end of the memory string, and a select gate transistor at the drain end, wherein the channel extends from the source end to the drain end, the set of memory cells comprises other memory cells and an adjacent memory cell, and the adjacent memory cell is adjacent to the select gate transistor;
during the charging up of the channel, increasing a control gate voltage of the adjacent memory cell, from a respective initial level to a respective peak level, and increasing a control gate voltage of the select gate transistor, from a respective initial level to a respective peak level; and
subsequently, decreasing the control gate voltage of the adjacent memory cell, from the respective peak level to a respective lower level and holding the control gate voltage of the adjacent memory cell at the respective lower level to erase the adjacent memory cell, and holding control gate voltages of the other memory cells at a respective fixed level to erase the other memory cells.

14. The method of claim 13 , wherein:
the charging up the channel comprises increasing a voltage at the source end.

15. The method of claim 13 , further comprising:
decreasing the control gate voltage of the select gate transistor from the respective initial level to an intermediate level which is between the respective peak level and the respective initial level; and
holding the control gate voltage of the select gate transistor at the intermediate level during the holding of the control gate voltage of the adjacent memory cell at the respective lower level and during the holding of the control gate voltages of the other memory cells at the respective fixed level.

16. The method of claim 13 , further comprising:
holding the control gate voltage of the select gate transistor at the respective peak level during the holding of the control gate voltage of the adjacent memory cell at the respective lower level and the holding of the control gate voltages of the other memory cells at the respective fixed level.

17. An apparatus, comprising:
a memory string comprising a set of memory cells between a source end of the memory string and a drain end of the memory string, wherein the drain end comprises a select gate transistor, and a channel extends between the source end and the drain end, the set of memory cells further comprises other memory cells and an adjacent memory cell, and the adjacent memory cell is adjacent to the select gate transistor;
means fo

Assignees

• Sandisk Technologies Llc

Inventors

• DIEP Vinh
• Yu Xuehong
• Zhang Zhengyi
• Dong Yingda

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5635 Primary

  Erasing circuits · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/3445

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title