Asynchronous data link

Patent metadata

Field	Value
Publication number	US-9921992-B2
Application number	US-201514981478-A
Country	US
Kind code	B2
Filing date	Dec 28, 2015
Priority date	Dec 29, 2014
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

A two-phase asynchronous transmission circuit for transmitting data over a wired interface according to a two-phase asynchronous protocol, the transmission circuit including: N data output lines, where N is an integer equal to 3 or more, wherein the transmission circuit is capable of transmitting N unique data symbols, each of the output lines being associated with a corresponding one of the N data symbols, and the transmission circuit is adapted to transmit each data symbol by applying a voltage transition to the corresponding output line independently of the voltage state of the other output lines.

First claim

What is claimed is:

1. A four-phase to two-phase asynchronous protocol converter comprising:
a two-phase asynchronous transmission circuit for transmitting data over a wired interface according to a two-phase asynchronous protocol, the transmission circuit comprising:
N data output lines, where N is an integer equal to 3 or more, wherein the transmission circuit is capable of transmitting N unique data symbols, each symbol corresponding to a binary value of at least two bits, each of the output lines being associated with a corresponding one of the N data symbols; and
a two-phase acknowledgement input line for receiving a two-phase acknowledgement signal comprising a voltage transition indicating that a data symbol has been successfully received and permitting a new data symbol to be transmitted, the transmission circuit being configured to transmit each data symbol by applying a voltage transition only to a corresponding output line independently of the voltage state of the other output lines; and

N data input lines, each of the input lines being associated with a corresponding one of the N data symbols, wherein the transmission circuit is configured to generate each symbol to be transmitted by detecting a first logic state on a corresponding one of the N data input lines.

2. The four-phase to two-phase converter of claim 1 , wherein the transmission circuit comprises, for each of the N input data lines, a logic circuit having an input coupled to the corresponding data input line and configured to generate a transition at its output in response to an active edge on the input data line, the active edge corresponding to either a falling edge or a rising edge.

3. The four-phase to two-phase converter of claim 2 , wherein each logic circuit comprises a flip-flop, and wherein:
said input of the logic circuit is a clock input of the flip-flop coupled to the corresponding input data line; and
the output of the flip-flop is coupled to a data input of the flip-flop via an inverter, the output of the flip-flip being connected to one of the output lines.

4. The four-phase to two-phase converter of claim 1 , further comprising:
a four-phase acknowledgement output line for transmitting a four-phase acknowledgement signal indicating that a data symbol has been successfully received; and
a four-phase acknowledgement generation circuit configured to generate the four-phase acknowledgement signal based on the two-phase acknowledgement signal.

5. The four-phase to two-phase converter of claim 4 , wherein the transmission circuit comprises, for each of the N input data lines, a logic circuit having an input coupled to the corresponding data input line and configured to generate a transition at its output in response to an active edge on the input data line, the active edge corresponding to either a falling edge or a rising edge and wherein the four-phase acknowledgement signal comprises, in response to the reception of each data symbol, the application of a second voltage state on the four-phase acknowledgement output line, and in response to the reception of a spacer by the four-phase to two-phase converter, the application of the first voltage state on the four-phase acknowledgement output line, and wherein the four-phase acknowledgement generation circuit is configured to apply the second voltage state on the four-phase acknowledgement output line when an active edge is detected on one of the N data input lines, and to apply the first voltage state on the four-phase acknowledgement output line when a transition is detected on one of the N data output lines and on the two-phase acknowledgement input line.

6. The four-phase to two-phase converter of claim 4 , wherein the four-phase acknowledgement generation circuit comprises a first XOR gate configured to apply the XOR function to the N data output lines and a second XOR gate having one input coupled to the output of the first XOR gate and another input coupled to the two-phase acknowledgement input line.

7. The four-phase to two-phase converter of claim 6 , wherein the four-phase acknowledgement generation circuit further comprises a NOR gate having N inputs coupled respectively to the N input lines, and an asymmetric C-element having a first input coupled to an output of the NOR gate and a second input coupled to an output of the second XOR gate via an inverter, wherein the asymmetric C-element is configured to generate a rising edge on the four-phase acknowledgement output line in response to rising edges at the outputs of the NOR gate and the inverter, and to generate a falling edge on the four-phase acknowledgement output line in response to a falling edge at the output of the NOR gate.

8. A four-phase to two-phase asynchronous protocol converter comprising:
a two-phase asynchronous transmission circuit for transmitting data over a wired interface according to a two-phase asynchronous protocol, the transmission circuit comprising N data output lines, where N is an integer equal to 3 or more, wherein the transmission circuit is capable of transmitting N unique data symbols, each symbol corresponding to binary value of at least two bits, each of the output lines being associated with a corresponding one of the N data symbols, the transmission circuit being configured to transmit each data symbol by applying a voltage transition only to a corresponding output line independently of the voltage state of the other output lines;
N data input lines, each of the input lines being associated with a corresponding one of the N data symbols, wherein the transmission circuit is configured to generate each symbol to be transmitted by detecting a first logic state on a corresponding one of the N data input lines;
a two-phase acknowledgement input line for receiving a two-phase acknowledgement signal comprising a voltage transition indicating that a data symbol has been successfully received and permitting a new data symbol to be transmitted, wherein the two-phase acknowledgement signal comprises a voltage transition on the two-phase acknowledgement input line;
a four-phase acknowledgement output line for transmitting a four-phase acknowledgement signal indicating that a data symbol has been successfully received; and
a four-phase acknowledgement generation circuit configured to generate the four-phase acknowledgement signal based on the two-phase acknowledgement signal, wherein the four-phase acknowledgement generation circuit comprises a first XOR gate configured to apply the XOR function to the N data output lines and a second XOR gate having one input coupled to the output of the first XOR gate and another input coupled to the two-phase acknowledgement input line.

9. A two-phase to four-phase asynchronous protocol converter comprising:
a two-phase asynchronous reception circuit for receiving data encoded according to a two-phase asynchronous protocol, the reception circuit comprising:
N data input lines, where N is an integer equal to 3 or more, wherein the reception circuit is capable of receiving N unique data symbols, each symbol corresponding to a binary value of at least two bits, each of the data input lines being associated with a corresponding one of the N data symbols; and
a two-phase acknowledgement output line for transmitting a two-phase acknowledgement signal comprising a voltage transition indicating that a data symbol has been successfully received and permitting a new data symbol to be transmitted, wherein the reception circuit is configured to generate each data symbol by detecting a voltage transition only on a corresponding one of the data input lines independently of the voltage state of the other data input lines; and

N data output lines, each of the data output lines being associated w

Assignees

• Commissariat Energie Atomique

Inventors

• Hilgemberg Pontes Julian
• Vivet Pascal

Classifications

• G06F13/4252

  using a handshaking protocol · CPC title

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• G06F15/7825

  Globally asynchronous, locally synchronous, e.g. network on chip · CPC title

• Y02B60/1235

  Cross-Sectional Technologies · mapped topic

• H03K19/0966

  Self-timed logic · CPC title