Peripheral interface circuit at host side and electronic system using the same

Patent metadata

Field	Value
Publication number	US-9804634-B2
Application number	US-201514589189-A
Country	US
Kind code	B2
Filing date	Jan 5, 2015
Priority date	Dec 3, 2014
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A peripheral interface circuit at host side and an electronic system using the same is disclosed. The peripheral interface circuit has a bus clock signal generator and a data register. The bus clock signal generator outputs a bus clock signal based on a host clock signal to be conveyed to a peripheral device via an interface bus as a reference for the peripheral device to output data. The data register receives the data output from the peripheral device and retrieved at the host side in accordance with the host clock signal. The bus clock signal generator adjusts the bus clock signal based on how the host clock signal is phase-asynchronous to the data output from the peripheral device and retrieved at the host side in accordance with the host clock signal.

First claim

What is claimed is:

1. A peripheral interface circuit at host side, comprising:
a bus clock signal generator, outputting a bus clock signal based on a host clock signal and a phase shift control signal to be conveyed to a peripheral device via an interface bus as a reference for the peripheral device to output data, wherein the host clock signal and the phase shift control signal are input to the bus clock signal generator; and
a data register, receiving the data output from the peripheral device and retrieved at the host side in accordance with the host clock signal,
wherein:
the bus clock signal generator adjusts the bus clock signal based on how the host clock signal is phase-asynchronous to the data output from the peripheral device and retrieved at the host side in accordance with the host clock signal.

2. The peripheral interface circuit at host side as claimed in claim 1 , wherein the bus clock signal generator adjusts the bus clock signal to make the data register receive the data output from the peripheral device and retrieved at the host side in accordance with the host clock signal within one clock cycle of the host clock signal.

3. The peripheral interface circuit at host side as claimed in claim 1 , wherein the bus clock signal generator shifts a phase of the bus clock signal to be earlier than a phase of the host clock signal.

4. The peripheral interface circuit at host side as claimed in claim 1 , wherein said asynchronous phase between the host clock signal and the data is due to a transmission delay, from the bus clock signal generator to the interface bus and then to the peripheral device, of the bus clock signal.

5. The peripheral interface circuit at host side as claimed in claim 1 , wherein said asynchronous phase between the host clock signal and the data is due to a delay from the peripheral device receiving the bus clock signal to the peripheral device generating the data and another delay for transmission of the data from the peripheral device to the data register.

6. The peripheral interface circuit at host side as claimed in claim 1 , wherein the bus clock signal generator selects one of the host clock signal and a plurality of phase-shifted clock signals generated from the host clock signal as the bus clock signal, wherein the phase-shifted clock signals each lead the host clock signal by k/N clock cycle, where k is a variable from 1 to (N−1).

7. The peripheral interface circuit at host side as claimed in claim 6 , wherein N equals 2 n and n is a natural number.

8. The peripheral interface circuit at host side as claimed in claim 1 , further comprising:
a first D-flip-flop, receiving a source clock signal and frequency dividing the source clock signal to generate the host clock signal.

9. The peripheral interface circuit at host side as claimed in claim 8 , wherein the bus clock signal generator comprises:
a first inverter, receiving the host clock signal;
a second D-flip-flop, frequency dividing an inverted signal of the source clock signal in accordance with the host clock signal;
a second inverter, receiving an output signal of the second D-flip-flop; and
a multiplexer,
wherein:
the second inverter outputs a first phase-shifted clock signal that leads the host clock signal by one quarter of a clock cycle of the host clock signal;
the first inverter outputs a second phase-shifted clock signal that leads the host clock signal by half a clock cycle of the host clock signal;
the second D-flip-flop outputs a third phase-shifted clock signal that leads the host clock signal by three quarters of one clock cycle of the host clock signal; and
the multiplexer receives the host clock signal and the first, the second and the third phase-shifted clock signals and selectively outputs one of the host clock signal and the first, the second and the third phase-shifted clock signals as the bus clock signal.

10. The peripheral interface circuit at host side as claimed in claim 1 , further comprising a multiplexer and a phase-locked loop, the phase-locked loop generating the host clock signal, wherein:
the phase-locked loop further generates a first phase-shifted clock signal, a second phase-shifted clock signal and a third phase-shifted clock signal;
the first phase-shifted clock signal leads the host clock signal by one quarter of a clock cycle of the host clock signal;
the second phase-shifted clock signal leads the host clock signal by half a clock cycle of the host clock signal;
the third phase-shifted clock signal leads the host clock signal by three quarters of one clock cycle of the host clock signal; and
the multiplexer receives the host clock signal and the first, the second and the third phase-shifted clock signals and selectively outputs one of the host clock signal and the first, the second and the third phase-shifted clock signals as the bus clock signal.

11. The peripheral interface circuit at host side as claimed in claim 1 , wherein the bus clock signal generator comprises:
a delay chain, phase shifting the host clock signal to generate the bus clock signal.

12. An electronic system, comprising:
a host, comprising:
a bus clock signal generator, outputting a bus clock signal based on a host clock signal and a phase shift control signal to be conveyed to a peripheral device via an interface bus as a reference for the peripheral device to output data, wherein the host clock signal and the phase shift control signal are input to the bus clock signal generator; and
a data register, receiving the data output from the peripheral device and retrieved at the host side in accordance with the host clock signal,

wherein the bus clock signal generator adjusts the bus clock signal based on how the host clock signal is phase-asynchronous to the data output from the peripheral device and retrieved at the host side in accordance with the host clock signal; and
a phase shift control module, generating the phase shift control signal for the bus clock signal generator to adjust the bus clock signal.

13. The electronic system as claimed in claim 12 , wherein the bus clock signal generator adjusts the bus clock signal to make the data register receive the data output from the peripheral device and retrieved at the host side in accordance with the host clock signal within one clock cycle of the host clock signal.

14. The electronic system as claimed in claim 12 , wherein the bus clock signal generator shifts a phase of the bus clock signal to lead a phase of the host clock signal.

15. The electronic system as claimed in claim 12 , wherein said asynchronous phase between the host clock signal and the data is due to a transmission delay, from the bus clock signal generator to the interface bus and then to the peripheral device, of the bus clock signal.

16. The electronic system as claimed in claim 12 , wherein said asynchronous phase between the host clock signal and the data is due to a delay from the peripheral device receiving the bus clock signal to the peripheral device generating the data and another delay for transmission of the data from the peripheral device to the data register.

17. The electronic system as claimed in claim 12 , wherein the bus clock signal generator selects one of the host clock signal and a plurality of phase-shifted clock signals generated from the host clock signal as the bus clock signal, wherein the phase-shifted clock signals each lead the host clock signal by k/N clock cycle, where k is a variable from 1 to (N−1), wherein N equals 2 n and n is a natural number.

18. The electronic system as

Assignees

• Via Alliance Semiconductor Co Ltd

Inventors

• Hui Zhiqiang
• Zhong Lingyan
• Dong Yunxing

Classifications

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F13/4226

  with asynchronous protocol · CPC title

• G06F13/4291 Primary

  using a clocked protocol · CPC title

• G06F13/102 Primary

  where the program performs an interfacing function, e.g. device driver (G06F13/105 takes precedence; contention policies within device drivers G06F9/4881; scheduling within device drivers G06F9/52) · CPC title