Self-aligned source and drain regions for semiconductor devices

Patent metadata

Field	Value
Publication number	US-9916984-B2
Application number	US-201715483273-A
Country	US
Kind code	B2
Filing date	Apr 10, 2017
Priority date	Mar 12, 2015
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses.

First claim

What is claimed is:

1. A method for forming a semiconductor device, comprising:
depositing a doped layer over a top of a two-dimensional material formed on a gate conductor, wherein the gate conductor is formed on a substrate;
adhering tape to the doped layer on top of the two-dimensional material; and
removing the tape to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions.

2. The method as recited in claim 1 , further comprising forming the two-dimensional material on the gate conductor by one of a deposition process or a transfer process.

3. The method as recited in claim 1 , wherein depositing the doped layer includes depositing the doped layer on sidewalls of the gate conductor.

4. The method as recited in claim 3 , wherein the doped layer remains on the sidewalls of the gate conductor after removing the tape to exfoliate the doped layer from the top of the two-dimensional material.

5. The method as recited in claim 1 , further comprising etching the gate conductor to form a gap between the sidewalk of the gate conductor and the vertical portions of the doped layer.

6. The method as recited in claim 5 , further comprising filling the gap with a dielectric material between the sidewalk of the gate conductor and the vertical portions of the doped layer.

7. The method as recited in claim 1 , wherein depositing the doped layer includes depositing the doped layer over the top of the two-dimensional material and along sidewalk of the gate conductor to form corners adjacent to the two-dimensional material, the corners providing yield points to exfoliate the doped layer.

8. The method as recited in claim 1 , wherein the two-dimensional material includes one of: graphene, pantacene, MoS 2 , WS 2 , boron nitride, mica, dichaicogenides or a complex oxide.

9. The method as recited in claim 1 , wherein depositing doped layer includes forming the source and drain regions by a process other than selective epitaxial growth.

10. A method for forming a semiconductor device, comprising:
depositing a doped layer along sidewalls of the gate conductor and over a top of a two-dimensional material formed on the gate conductor;
adhering tape to the doped layer on op of the two-dimensional material; and
removing the tape to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in recesses on opposite sides of the gate conductor.

11. The method as recited in claim 10 , further comprising forming the two-dimensional material by one of a deposition process or a transfer process.

12. The method as recited in claim 10 , wherein the doped layer remains on the sidewalls of the gate conductor after removing the tape to exfoliate the doped layer from the top of the two-dimensional material.

13. The method as recited in claim 10 , further comprising etching the gate conductor to form a gap between the sidewalls of the gate conductor and vertical portions of the doped layer along the sidewalls of the gate conductor.

14. The method as recited in claim 13 , further comprising filling the gap with a dielectric material between the sidewalls of the gate conductor and the vertical portions of the doped layer.

15. The method as recited in claim 10 , wherein the doped layer forms corners over the sidewalk of the gate conductor adjacent to the two-dimensional material, the corners providing yield points to exfoliate the doped layer.

16. The method as recited in claim 10 , wherein the two-dimensional material includes one of: graphene, pantacene, MoS 2 , WS 2 , boron nitride, mica, dichalcogenides or a complex oxide.

17. The method as recited in claim 10 , wherein the recesses on opposite sides of the gate conductor are etched into the substrate partially below the gate conductor.

18. The method as recited in claim 17 , further comprising forming a gate dielectric on the substrate, wherein the gate dielectric is between the gate conductor and the substrate.

19. The method as recited in claim 18 , wherein the gate dielectric is between the gate conductor and the source and drain regions in the recesses on opposite sides of the conductor.

20. The method as recited in claim 18 , wherein the source and drain regions are monocrystalline structures or multi-crystal structures.

Assignees

• IBM

Inventors

• De Souza Joel P
• Hekmatshoartabari Bahman
• Kim Jeehwan
• Maurer Siegfried L
• Sadana Devendra K

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P50/262

  by physical means only · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P32/1408

  from or through or into an external applied layer, e.g. photoresist or nitride layers · CPC title